"A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid ..."

Gregory K. Chen et al. (2015)

> Home

Details and statistics

DOI: 10.1109/JSSC.2014.2369508

access: closed

type: Journal Article

metadata version: 2022-02-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/ChenAKSMHAKDB15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/ChenAKSMHAKDB15
Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar:
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(1): 59-67 (2015)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.