"A 4.2GHz 0.3mm2 256kb Dual-V_cc SRAM Building Block in 65nm CMOS."

Muhammad M. Khellah et al. (2006)

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DOI: 10.1109/ISSCC.2006.1696323

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-26

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Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 4.2GHz 0.3mm2 256kb Dual-V_cc SRAM Building Block in 65nm CMOS. ISSCC 2006: 2572-2581

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