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Franck Julien
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2020 – today
- 2023
- [c8]Lucas Antunes Tambara, Pascal Masson, Julien Amouroux, Stéphane Monfray, Julien Dura, Frederic Gianesello, Julien Babic, Romain Debroucke, Loic Welter, Siddhartha Dhar, Bernadette Gros, Clement Charbuillet, Franck Julien, Guillaume Bertrand, Arnaud Régnier, Alain Fleury:
Notched gate MOSFET for capacitance reduction in RF SOI technology. DTTIS 2023: 1-4 - 2022
- [c7]Paul Devoge, Hassen Aziza, Philippe Lorenzini, Pascal Masson, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel:
A Schmitt trigger to benchmark the performance of a new zero-cost transistor. ICECS 2022 2022: 1-4 - [c6]Paul Devoge, Hassen Aziza, Philippe Lorenzini, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel:
Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor. ISCAS 2022: 761-764 - 2021
- [c5]Paul Devoge, Hassen Aziza, Philippe Lorenzini, Franck Julien, Abderrezak Marzaki, Alexandre Malherbe, Marc Mantelli, Thomas Sardin, Sébastien Haendler, Arnaud Régnier, Stephan Niel:
Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology. DTIS 2021: 1-5
2010 – 2019
- 2015
- [c4]Jordan Innocenti, Franck Julien, Jean-Michel Portal, Laurent Lopez, Q. Hubert, Pascal Masson, Jacques Sonzogni, Stephan Niel, Arnaud Régnier:
Layout optimizations to decrease internal power and area in digital CMOS standard cells. MIPRO 2015: 1582-1587 - [c3]Jordan Innocenti, Loïc Welter, Nicolas Borrel, Franck Julien, Jean-Michel Portal, Jacques Sonzogni, Laurent Lopez, Pascal Masson, Stephan Niel, Philippe Dreux, Julia Castellan:
Dynamic current reduction of CMOS digital circuits through design and process optimization. PATMOS 2015: 77-81 - 2014
- [c2]Jordan Innocenti, Loic Welter, Franck Julien, Laurent Lopez, Jacques Sonzogni, Stephan Niel, Arnaud Régnier, Emmanuel Paire, Karen Labory, Eric Denis, Jean-Michel Portal, Pascal Masson:
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology. MWSCAS 2014: 897-900 - 2011
- [j1]Y. Joly, Laurent Lopez, Jean-Michel Portal, Hassen Aziza, Jean-Luc Ogier, Y. Bert, Franck Julien, Pascal Fornara:
Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress. Microelectron. Reliab. 51(9-11): 1561-1563 (2011) - [c1]Y. Joly, L. Truphemus, Laurent Lopez, Jean-Michel Portal, Hassen Aziza, Franck Julien, Pascal Fornara:
Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area. ISCAS 2011: 2549-2552
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