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ORCIDLeonid Yavits
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2020 – today
- 2024
[j29]Esteban Garzón
, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits:
FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access 12: 13923-13943 (2024)- [j28]Zuher Jahshan, Esteban Garzón, Leonid Yavits:
ViRAL: Vision Transformer Based Accelerator for ReAL Time Lineage Assignment of Viral Pathogens. IEEE Access 12: 28353-28368 (2024) - [j27]Eldar Cohen, Leonid Yavits, Benjamin M. Zaidel, Alexander Fish, Itamar Levi:
CoNfasTT: A Configurable, Scalable, and Fast Dual Mode Logic-Based NTT Design. IEEE Access 12: 150486-150501 (2024) - [j26]Zuher Jahshan, Leonid Yavits:
ViTAL: Vision TrAnsformer based Low coverage SARS-CoV-2 lineage assignment. Bioinform. 40(3) (2024) - [j25]Leonid Yavits:
DRAMA: Commodity DRAM Based Content Addressable Memory. IEEE Comput. Archit. Lett. 23(1): 65-68 (2024) - [j24]Zuher Jahshan, Leonid Yavits:
MajorK: Majority Based kmer Matching in Commodity DRAM. IEEE Comput. Archit. Lett. 23(1): 83-86 (2024) - [j23]Itay Merlin, Esteban Garzón, Alexander Fish, Leonid Yavits:
DIPER: Detection and Identification of Pathogens Using Edit Distance-Tolerant Resistive CAM. IEEE Trans. Computers 73(10): 2463-2473 (2024) - [c16]Netanel Shavit, Inbal Stanger, Ramiro Taco, Leonid Yavits, Alexander Fish:
Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications. PRIME 2024: 1-4 - 2023
- [j22]Esteban Garzón, Leonid Yavits, Giovanni Finocchio, Mario Carpentieri, Adam Teman, Marco Lanuzza:
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access 11: 16812-16819 (2023) - [j21]Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits:
AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 408-421 (2023) - [j20]Esteban Garzón, Roman Golman, Marco Lanuzza, Adam Teman, Leonid Yavits:
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3867-3871 (2023) - [j19]Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky:
ClaPIM: Scalable Sequence Classification Using Processing-in-Memory. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1347-1357 (2023) - [c15]Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza:
STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS 2023: 1-4 - [c14]Zuher Jahshan, Itay Merlin, Esteban Garzón, Leonid Yavits:
DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification. MICRO 2023: 1453-1465 - [i21]Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky:
ClaPIM: Scalable Sequence CLAssification using Processing-In-Memory. CoRR abs/2302.08284 (2023) - [i20]Leonid Yavits:
DRAMA: Commodity DRAM based Content Addressable Memory. CoRR abs/2312.15527 (2023) - 2022
- [j18]Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits:
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access 10: 28080-28093 (2022) - [j17]Esteban Garzón, Adam Teman, Marco Lanuzza, Leonid Yavits:
AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro 42(6): 67-75 (2022) - [j16]Leonid Yavits, Roman Kaplan, Ran Ginosar:
GIRAF: General Purpose In-Storage Resistive Associative Framework. IEEE Trans. Parallel Distributed Syst. 33(2): 276-287 (2022) - [c13]Robert Hanhan, Esteban Garzón, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits:
EDAM: edit distance tolerant approximate matching content addressable memory. ISCA 2022: 495-507 - [i19]Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky:
FiltPIM: In-Memory Filter for DNA Sequencing. CoRR abs/2205.15140 (2022) - [i18]Zuher Jahshan, Leonid Yavits:
CoViT: Real-time phylogenetics for the SARS-CoV-2 pandemic using Vision Transformers. CoRR abs/2208.05004 (2022) - 2021
- [c12]Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky:
FiltPIM: In-Memory Filter for DNA Sequencing. ICECS 2021: 1-4 - [i17]Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits:
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR abs/2111.09747 (2021) - 2020
- [c11]Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu:
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. ICCD 2020: 187-196 - [c10]Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish:
Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. ISCAS 2020: 1-5 - [c9]Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish:
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. ISCAS 2020: 1-5 - [c8]Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish:
Dual Mode Logic Address Decoder. ISCAS 2020: 1-5 - [c7]Roman Kaplan, Leonid Yavits, Ran Ginosar:
BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. SYSTOR 2020: 36-48 - [i16]Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu:
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. CoRR abs/2010.02825 (2020)
2010 – 2019
- 2019
- [j15]Roman Kaplan, Leonid Yavits, Ran Ginosar:
RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping. IEEE Micro 39(4): 44-54 (2019) - [c6]Roman Kaplan, Leonid Yavits, Ran Ginosar:
POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. PACT 2019: 459-460 - [c5]Leonid Yavits, Roman Kaplan, Ran Ginosar:
POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework. PACT 2019: 477-478 - [i15]Leonid Yavits, Roman Kaplan, Ran Ginosar:
AIDA: Associative DNN Inference Accelerator. CoRR abs/1901.04976 (2019) - [i14]Roman Kaplan, Leonid Yavits, Ran Ginosar:
BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. CoRR abs/1901.05959 (2019) - 2018
- [j14]Leonid Yavits, Ran Ginosar:
Accelerator for Sparse Machine Learning. IEEE Comput. Archit. Lett. 17(1): 21-24 (2018) - [j13]Leonid Yavits, Roman Kaplan, Ran Ginosar:
Enabling Full Associativity with Memristive Address Decoder. IEEE Micro 38(5): 32-40 (2018) - [i13]Leonid Yavits, Roman Kaplan, Ran Ginosar:
PRINS: Resistive CAM Processing in Storage. CoRR abs/1805.09612 (2018) - [i12]Roman Kaplan, Leonid Yavits, Ran Ginosar:
RASSA: Resistive Accelerator for Approximate Long Read DNA Mapping. CoRR abs/1809.01127 (2018) - 2017
- [j12]Leonid Yavits, Uri C. Weiser, Ran Ginosar:
Resistive Address Decoder. IEEE Comput. Archit. Lett. 16(2): 141-144 (2017) - [j11]Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. IEEE Micro 37(4): 20-28 (2017) - [j10]Roman Kaplan, Leonid Yavits, Ran Ginosar:
From Processing-in-Memory to Processing-in-Storage. Supercomput. Front. Innov. 4(3): 99-116 (2017) - [i11]Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. CoRR abs/1701.04723 (2017) - [i10]Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar:
MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. CoRR abs/1705.06923 (2017) - [i9]Leonid Yavits, Amir Morad, Ran Ginosar:
The Effect of Temperature on Amdahl Law in 3D Multicore Era. CoRR abs/1705.07280 (2017) - [i8]Leonid Yavits, Amir Morad, Ran Ginosar:
Cache Hierarchy Optimization. CoRR abs/1705.07281 (2017) - [i7]Leonid Yavits, Amir Morad, Ran Ginosar:
Sparse Matrix Multiplication On An Associative Processor. CoRR abs/1705.07282 (2017) - [i6]Leonid Yavits, Ran Ginosar:
Sparse Matrix Multiplication on CAM Based Accelerator. CoRR abs/1705.09937 (2017) - 2016
- [j9]Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar:
Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. 12(4): 57:1-57:22 (2016) - [j8]Leonid Yavits, Amir Morad, Ran Ginosar:
The Effect of Temperature on Amdahl Law in 3D Multicore Era. IEEE Trans. Computers 65(6): 2010-2013 (2016) - [c4]Roman Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar:
Deduplication in resistive content addressable memory based solid state drive. PATMOS 2016: 100-106 - [i5]Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser:
Convex Optimization of Real Time SoC. CoRR abs/1601.07815 (2016) - [i4]Leonid Yavits, Amir Morad, Ran Ginosar:
Effect of Data Sharing on Private Cache Design in Chip Multiprocessors. CoRR abs/1602.01329 (2016) - 2015
- [j7]Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar:
Resistive Associative Processor. IEEE Comput. Archit. Lett. 14(2): 148-151 (2015) - [j6]Leonid Yavits, Amir Morad, Ran Ginosar:
Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. IEEE Trans. Computers 64(2): 368-381 (2015) - [j5]Leonid Yavits, Amir Morad, Ran Ginosar:
Sparse Matrix Multiplication On An Associative Processor. IEEE Trans. Parallel Distributed Syst. 26(11): 3175-3183 (2015) - 2014
- [j4]Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. IEEE Comput. Archit. Lett. 13(1): 37-40 (2014) - [j3]Leonid Yavits, Amir Morad, Ran Ginosar:
Cache Hierarchy Optimization. IEEE Comput. Archit. Lett. 13(2): 69-72 (2014) - [j2]Leonid Yavits, Amir Morad, Ran Ginosar:
The effect of communication and synchronization on Amdahl's law in multicore systems. Parallel Comput. 40(1): 1-16 (2014) - [j1]Amir Morad, Leonid Yavits, Ran Ginosar:
GP-SIMD Processing-in-Memory. ACM Trans. Archit. Code Optim. 11(4): 53:1-53:26 (2014) - [c3]Amir Morad, Leonid Yavits, Ran Ginosar:
Efficient Dense and Sparse Matrix Multiplication on GP-SIMD. PATMOS 2014: 1-8 - [c2]Amir Morad, Leonid Yavits, Ran Ginosar:
Convex optimization of resource allocation in asymmetric and heterogeneous SoC. PATMOS 2014: 1-8 - 2013
- [c1]Leonid Yavits, Amir Morad, Ran Ginosar:
3D cache hierarchy optimization. 3DIC 2013: 1-5 - [i3]Leonid Yavits, Amir Morad, Ran Ginosar:
The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems. CoRR abs/1306.3302 (2013) - [i2]Leonid Yavits, Amir Morad, Ran Ginosar:
Thermal analysis of 3D associative processor. CoRR abs/1307.3853 (2013) - [i1]Leonid Yavits, Amir Morad, Ran Ginosar:
3D Cache Hierarchy Optimization. CoRR abs/1311.1667 (2013)
Coauthor Index
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last updated on 2024-12-10 21:48 CET by the dblp team
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