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2020 – today
- 2024
[j25]Jun-Sheng Ng
, Juncheng Chen, Nay Aung Kyaw, Kwen-Siong Chong, Bah-Hwee Gwee:
Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1959-1963 (2024)- [c54]Juncheng Chen, Han Zhang, Zishuo Yang, Yicheng Xu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix. ISCAS 2024: 1-5 - [c53]Rouli Fang, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Wei Shu, Sun-Yang Tay, Joseph Sylvester Chang:
A Novel Multi-Error-Lock-Trace (MELT) Test Structure for SET/SEU Characterization of Radiation-Hardened-By-Design Cells. MWSCAS 2024: 37-41 - 2023
- [c52]Jun-Sheng Ng, Juncheng Chen, Si Wu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. ISCAS 2023: 1-5 - 2022
- [j24]Xvpeng Zhang, Bingqiang Liu, Yaqi Zhao, Xiaoyu Hu, Zixuan Shen, Zhaoxia Zheng, Zhenglin Liu, Kwen-Siong Chong, Guoyi Yu, Chao Wang, Xuecheng Zou:
Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices. Sensors 22(23): 9160 (2022) - [j23]Jipeng Wang, Zixuan Peng, Yi Zhan, Yujie Li, Guoyi Yu, Kwen-Siong Chong, Chao Wang:
A High-Accuracy and Energy-Efficient CORDIC Based Izhikevich Neuron With Error Suppression and Compensation. IEEE Trans. Biomed. Circuits Syst. 16(5): 807-821 (2022) - [j22]Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1144-1157 (2022) - [c51]Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Zhili Zou, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
Incremental Linear Regression Attack. AsianHOST 2022: 1-4 - [c50]Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee:
Non-profiling based Correlation Optimization Deep Learning Analysis. ISCAS 2022: 2246-2250 - [c49]Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. ISCAS 2022: 2256-2260 - 2021
- [j21]Kwen-Siong Chong, Jun-Sheng Ng, Juncheng Chen, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Joseph Sylvester Chang, Bah-Hwee Gwee:
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 343-356 (2021) - [j20]Jiajun Wu, Xuan Huang, Le Yang, Jipeng Wang, Bingqiang Liu, Ziyuan Wen, Juhui Li, Guoyi Yu, Kwen-Siong Chong, Chao Wang:
An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 725-738 (2021) - [j19]Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee:
A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 2122-2126 (2021) - [j18]Juncheng Chen, Jun-Sheng Ng, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures. IEEE Trans. Inf. Forensics Secur. 16: 3767-3779 (2021) - [c48]Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee:
Normalized Differential Power Analysis - for Ghost Peaks Mitigation. ISCAS 2021: 1-5 - [c47]Zixuan Peng, Jipeng Wang, Yi Zhan, Run Min, Guoyi Yu, Jianwen Luo, Kwen-Siong Chong, Chao Wang:
A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron. NEWCAS 2021: 1-4 - 2020
- [c46]Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee:
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. APCCAS 2020: 161-164 - [c45]Jiajun Wu, Xuan Huang, Le Yang, Liang Wang, Jipeng Wang, Zuozhu Liu, Kwen-Siong Chong, Shaowei Lin, Chao Wang:
An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity. A-SSCC 2020: 1-4 - [c44]Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang:
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller. ISCAS 2020: 1-5 - [c43]Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee:
A Secure Data-Toggling SRAM for Confidential Data Protection. ISCAS 2020: 1 - [c42]Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. ISCAS 2020: 1-5 - [c41]Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee:
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). ISCAS 2020: 1-5 - [c40]Weng-Geng Ho, Ali Akbar Pammu, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee:
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications. ISOCC 2020: 173-174
2010 – 2019
- 2019
- [j17]Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee:
A Secure Data-Toggling SRAM for Confidential Data Protection. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4186-4199 (2019) - [j16]Ali Akbar Pammu, Kwen-Siong Chong, Yi Wang, Bah-Hwee Gwee:
A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information. IEEE Trans. Dependable Secur. Comput. 16(3): 376-387 (2019) - [j15]Ali Akbar Pammu, Weng-Geng Ho, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee:
A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor. IEEE Trans. Inf. Forensics Secur. 14(4): 1023-1036 (2019) - [c39]Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang:
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. AsianHOST 2019: 1-7 - [c38]Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, W. Shu, Joseph S. Chang, Bah-Hwee Gwee:
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. ISCAS 2019: 1-5 - [c37]Weng-Geng Ho, Ali Akbar Pammu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee:
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications. SoCC 2019: 86-91 - 2018
- [j14]Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang:
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 196-200 (2018) - [c36]Weng-Geng Ho, Zixian Zheng, Kwen-Siong Chong, Bah-Hwee Gwee:
A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation. DSP 2018: 1-5 - [c35]Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin, Wei Shu, Joseph S. Chang:
Single-Event-Transient Resilient Memory for DSP in Space Applications. DSP 2018: 1-5 - [c34]Wei Shu, Jize Jiang, Kwen-Siong Chong, Joseph Sylvester Chang:
Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things. DSP 2018: 1-4 - 2017
- [j13]Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 402-415 (2017) - [c33]James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee:
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer. ISCAS 2017: 1-4 - [c32]Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee:
Highly secured state-shift local clock circuit to countermeasure against side channel attack. ISCAS 2017: 1-4 - 2016
- [c31]Ali Akbar Pammu, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Nan Liu, Bah-Hwee Gwee:
Success rate model for fully AES-128 in correlation power analysis. APCCAS 2016: 115-118 - [c30]Ali Akbar Pammu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee:
Interceptive side channel attack on AES-128 wireless communications for IoT applications. APCCAS 2016: 650-653 - [c29]Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. DATE 2016: 850-853 - [c28]Jize Jiang, Wei Shu, Kwen-Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Joseph Sylvester Chang, Jingyuan Liu:
Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process. ISCAS 2016: 5-8 - [c27]Weng-Geng Ho, Kyaw Zwa Lwin Ne, N. Prashanth Srinivas, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee:
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. ISCAS 2016: 698-701 - [c26]Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang:
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. ISCAS 2016: 966-969 - [c25]Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. ISCAS 2016: 1762-1765 - [c24]Weng-Geng Ho, Ali Akbar Pammu, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee:
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. ISIC 2016: 1-4 - [c23]Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee:
Highly secured arithmetic hiding based S-Box on AES-128 implementation. ISIC 2016: 1-4 - [c22]Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee:
Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture. NAS 2016: 1-7 - 2015
- [j12]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. IET Circuits Devices Syst. 9(4): 309-318 (2015) - [c21]Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang:
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). ISCAS 2015: 1913-1916 - [c20]Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. ISCAS 2015: 2589-2592 - 2014
- [j11]Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee:
Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing. Circuits Syst. Signal Process. 33(10): 3317-3329 (2014) - [j10]Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 989-1002 (2014) - [c19]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. APCCAS 2014: 5-8 - [c18]Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho:
Synthesis of asynchronous QDI circuits using synchronous coding specifications. ISCAS 2014: 153-156 - [c17]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin:
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. ISIC 2014: 320-323 - [c16]Joseph S. Chang, Kwen-Siong Chong, Wei Shu, Tong Lin, Jize Jiang, Ne Kyaw Zwa Lwin, Yang Kang:
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process. MWSCAS 2014: 821-824 - 2013
- [j9]Kok-Leong Chang, Joseph S. Chang, Bah-Hwee Gwee, Kwen-Siong Chong:
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. IEEE J. Emerg. Sel. Topics Circuits Syst. 3(1): 23-34 (2013) - [j8]Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. IEEE J. Solid State Circuits 48(2): 573-586 (2013) - [c15]Jaeyoung Kim, Kwen-Siong Chong, Joseph Sylvester Chang, Pinaki Mazumder:
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS. ACM Great Lakes Symposium on VLSI 2013: 83-88 - [c14]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. ISCAS 2013: 353-356 - [c13]Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. ISCAS 2013: 3022-3025 - 2012
- [j7]Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang:
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. IEEE J. Solid State Circuits 47(3): 769-780 (2012) - [c12]Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. ISCAS 2012: 492-495 - [c11]Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A comparative study on asynchronous Quasi-Delay-Insensitive templates. ISCAS 2012: 1819-1822 - [c10]Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. ISCAS 2012: 1835-1838 - [c9]Kwen-Siong Chong, Joseph S. Chang, Idongesit E. Ebong, Yalcin Yilmaz, Pinaki Mazumder:
Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques. ISED 2012: 116-119 - 2011
- [c8]Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low-power dual-rail inputs write method for bit-interleaved memory cells. ISCAS 2011: 325-328 - [c7]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang:
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. ISCAS 2011: 1936-1939
2000 – 2009
- 2009
- [j6]Bah-Hwee Gwee, Joseph S. Chang, Yiqiong Shi, Chien-Chung Chua, Kwen-Siong Chong:
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7): 1349-1359 (2009) - [c6]Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. ISCAS 2009: 3162-3165 - 2007
- [j5]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Design of several asynchronous-logic macrocells for a low-voltage micropower cell library. IET Circuits Devices Syst. 1(2): 161-169 (2007) - [j4]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low energy 16-bit Booth leapfrog array multiplier using dynamic adders. IET Circuits Devices Syst. 1(2): 170-174 (2007) - [j3]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. IEEE J. Solid State Circuits 42(9): 2034-2045 (2007) - [c5]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Low Energy FFT/IFFT Processor for Hearing Aids. ISCAS 2007: 1169-1172 - 2006
- [j2]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 853-857 (2006) - 2005
- [j1]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A micropower low-voltage multiplier with reduced spurious switching. IEEE Trans. Very Large Scale Integr. Syst. 13(2): 255-265 (2005) - [c4]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage micropower multipliers with reduced spurious switching. ISCAS (4) 2005: 4078-4081 - 2004
- [c3]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. ISCAS (2) 2004: 437-440 - 2002
- [c2]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage micropower asynchronous multiplier for hearing instruments. ISCAS (1) 2002: 865-868 - [c1]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage asynchronous adders for low power and high speed applications. ISCAS (1) 2002: 873-876
Coauthor Index
Joseph Sylvester Chang
aka: Joseph S. Chang
aka: Joseph S. Chang
[j25] [c54] [c52] [j22] [c51] [c50] [c49] [j21] [j19] [j18] [c48] [c46] [c43] [c42] [c41] [c40] [j17] [j16] [j15] [c39] [c38] [c37] [j14] [c36] [j13] [c33] [c32] [c31] [c30] [c29] [c27] [c25] [c24] [c23] [c22] [j12] [c21] [c20] [j11] [j10] [c19] [c18] [c17] [j9] [j8] [c14] [c13] [j7] [c12] [c11] [c10] [c8] [c7] [j6] [c6] [j5] [j4] [j3] [c5] [j2] [j1] [c4] [c3] [c2] [c1]
Ne Kyaw Zwa Lwin
aka: Kyaw Zwa Lwin Ne
aka: Kyaw Zwa Lwin Ne
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