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2020 – today
- 2024
[j29]Saad Pola
, Marko Jovanovic, Maher A. Azzouz, Mitra Mirhassani:
Cyber Resiliency Enhancement of Overcurrent Relays in Distribution Systems. IEEE Trans. Smart Grid 15(4): 4063-4076 (2024)- [j28]Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid:
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1423-1435 (2024) - 2023
- [j27]Foroogh Behnia, Habib Zare Ahmadabadi, Beth-Anne Schuelke Leech, Mitra Mirhassani:
Developing a fuzzy optimized model for selecting a maintenance strategy in the paper industry: An integrated FGP-ANP-FMEA approach. Expert Syst. Appl. 232: 120899 (2023) - [j26]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1724-1728 (2023) - [j25]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1377-1388 (2023) - [j24]Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mohammed A. S. Khalid, Mitra Mirhassani:
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1509-1522 (2023) - [c34]Edris Zaman Farsa, Moslem Heidarpur, Arash Ahmadi, Mitra Mirhassani:
High-Performance FPGA Implementation of Fully Connected Networks of SAM Neurons. ISCAS 2023: 1-5 - 2022
- [j23]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
A High-Accuracy Digital Implementation of the Morris-Lecar Neuron With Variable Physiological Parameters. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4138-4142 (2022) - [j22]Moslem Heidarpur, Mitra Mirhassani:
Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation". IEEE Trans. Very Large Scale Integr. Syst. 30(1): 112 (2022) - [j21]Hamidreza Esmaeili Taheri, Mitra Mirhassani:
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach. IEEE Trans. Very Large Scale Integr. Syst. 30(3): 315-324 (2022) - [j20]Madhan Thirumoorthi, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid:
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 603-614 (2022) - [c33]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
Selective Input Sparsity in Spiking Neural Networks for Pattern Classification. ISCAS 2022: 799-803 - [c32]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
A Low-Resource Digital Implementation of the Fitzhugh-Nagumo Neuron. PRIME 2022: 369-372 - 2021
- [j19]Neda Rezaei, Mitra Mirhassani:
Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference. Microelectron. J. 113: 105087 (2021) - [j18]Moslem Heidarpur, Mitra Mirhassani:
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 667-676 (2021) - [j17]Madhan Thirumoorthi, Marko Jovanovic, Mitra Mirhassani, Mohammed A. S. Khalid:
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1912-1921 (2021) - 2020
- [j16]Alexander J. Leigh, Mitra Mirhassani, Roberto Muscedere:
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model. IEEE Trans. Circuits Syst. 67-II(12): 3377-3381 (2020) - [c31]Alexander J. Leigh, Mitra Mirhassani, Roberto Muscedere:
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model. ISCAS 2020: 1-2
2010 – 2019
- 2019
- [j15]Iman Y. Taha, Mitra Mirhassani:
A Varactor-Less DCO With 7GHz Tuning Range for 77GHz Automotive Radars. IEEE Access 7: 72469-72481 (2019) - [j14]Bahar Youssefi, Alexander J. Leigh, Mitra Mirhassani, Q. M. Jonathan Wu:
Tunable Neuron With PWL Approximation Based on the Minimum Operator. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 387-391 (2019) - [j13]Iman Y. Taha, Mitra Mirhassani:
A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2260-2271 (2019) - 2018
- [c30]Bahar Youssefi, Alexander J. Leigh, Mitra Mirhassani, Q. M. Jonathan Wu:
Hardware Realization of Mixed-Signal Neural Networks with Modular Synapse-Neuron arrays. ISCAS 2018: 1-5 - [c29]Iman Y. Taha, Mitra Mirhassani, Arezoo Emadi:
A Monotonically Linear DCO for 77 GHz Automotive Radars. MWSCAS 2018: 77-80 - [c28]Babak Zamanlooy, Mitra Mirhassani, Majid Ahmadi:
Review of Arithmetic Operations Using the Continuous Valued Number System. MWSCAS 2018: 324-327 - 2017
- [j12]Seyed Mahmoud Anisheh, Hossein Shamsi, Mitra Mirhassani:
Positive feedback technique and split-length transistors for DC-gain enhancement of two-stage op-amps. IET Circuits Devices Syst. 11(6): 605-612 (2017) - [j11]Babak Zamanlooy, Mitra Mirhassani:
Mixed-signal VLSI neural network based on Continuous Valued Number System. Neurocomputing 221: 15-23 (2017) - [j10]Babak Zamanlooy, Mitra Mirhassani:
An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 894-906 (2017) - [c27]Esrafil Jedari, Rashid Rashidzadeh, Mitra Mirhassani, Majid Ahmadi:
Two-electrode ECG measurement circuit using a feed forward CMRR enhancement method. CCECE 2017: 1-4 - [c26]Yuan Jing, Bahar Youssefi, Mitra Mirhassani, Roberto Muscedere:
An efficient FPGA implementation of Optical Character Recognition for License Plate Recognition. CCECE 2017: 1-4 - [c25]Roberto Muscedere, Mitra Mirhassani:
A software tool for generating optimized multipartite table parameters. CCECE 2017: 1-4 - [c24]Iman Y. Taha, Mitra Mirhassani:
A CMOS differential DCO with amplitude stabilization for 24GHz automotive radars. CCECE 2017: 1-4 - [c23]Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi:
A neural network architecture using high resolution multiplying digital to analog converters. MWSCAS 2017: 1454-1457 - 2016
- [c22]Shaghayegh Gomar, Mitra Mirhassani, Majid Ahmadi:
Precise digital implementations of hyperbolic tanh and sigmoid function. ACSSC 2016: 1586-1589 - [c21]Shaghayegh Gomar, Mitra Mirhassani, Majid Ahmadi, Mehrdad Saif:
A digital neuromorphic circuit for neural-glial interaction. IJCNN 2016: 213-218 - [c20]Hadis Takaloo, Arash Ahmadi, Mitra Mirhassani, Majid Ahmadi:
Analog cellular neural network for application in physical unclonable functions. ISCAS 2016: 2635-2638 - [c19]Iman Y. Taha, Mitra Mirhassani:
A 24GHz Digitally Controlled Oscillator for automotive radar in 65nm CMOS. ISCAS 2016: 2767-2770 - [c18]Bahar Youssefi, Mitra Mirhassani, Q. M. Jonathan Wu:
Efficient mixed-signal synapse multipliers for multi-layer feed-forward neural networks. MWSCAS 2016: 1-4 - 2015
- [j9]Babak Zamanlooy, Mitra Mirhassani:
CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2540-2551 (2015) - [c17]Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi:
A modular mixed-signal CVNS neural network architecture. IJCNN 2015: 1-6 - 2014
- [j8]Babak Zamanlooy, Mitra Mirhassani:
Area-efficient robust Madaline based on continuous valued number system. Neurocomputing 140: 128-145 (2014) - [j7]Babak Zamanlooy, Mitra Mirhassani:
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 39-48 (2014) - [c16]Shaghayegh Gomar, Arash Ahmadi, Shahpour Alirezaee, Majid Ahmadi, Mitra Mirhassani:
A low cost biomimetic implementation of a CPG based on AdEx neuron model. ICECS 2014: 666-669 - [c15]Babak Zamanlooy, Mitra Mirhassani:
Area efficient low-sensitivity lumped madaline based on Continuous Valued Number System. ISCAS 2014: 2241-2244 - [c14]Iman Y. Taha, Mitra Mirhassani:
A temperature compensated relaxation oscillator for SoC implementations. NEWCAS 2014: 373-376 - 2012
- [j6]Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi:
A Prototype CVNS Distributed Neural Network Using Synapse-Neuron Modules. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(7): 1482-1490 (2012) - [j5]Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi:
Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 750-754 (2012) - [c13]Ashley Novak, Farinoush Saffar, Mitra Mirhassani, Huapeng Wu:
Current mode multiple-valued adder for cryptography processors. ISCAS 2012: 1460-1463 - [c12]Babak Zamanlooy, Ashley Novak, Mitra Mirhassani:
Complexity Study of the Continuous Valued Number System Adders. ISMVL 2012: 116-121 - [c11]Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi:
A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks. ISMVL 2012: 250-255 - [c10]Babak Zamanlooy, Mitra Mirhassani:
Efficient hardware implementation of threshold neural networks. NEWCAS 2012: 1-4 - 2011
- [j4]Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien:
Error Recovery in Continuous Valued Number System. J. Circuits Syst. Comput. 20(8): 1449-1476 (2011) - [j3]Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi:
CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1517-1521 (2011) - [c9]Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi:
A study on resistive-type truncated CVNS Distributed Neural Networks. ISCAS 2011: 2685-2688 - 2010
- [j2]Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi:
Resistive-Type CVNS Distributed Neural Networks With Improved Noise-to-Signal Ratio. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 793-797 (2010) - [c8]Mitra Mirhassani, Babak Zamanlooy:
System-level design of low complexity CVNS feed forward neural network. ISCAS 2010: 2578-2581
2000 – 2009
- 2009
- [c7]Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi:
An area-speed efficient method for current mode analog to digital converters. ECCTD 2009: 201-204 - [c6]Mitra Mirhassani:
Mixed-signal CVNS adder for two-operand binary addition. EIT 2009: 226-229 - [c5]Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi:
Current-mode Multiple-valued Dynamic Memory. ISCAS 2009: 3058-3061 - [c4]Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi:
16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin. ISMVL 2009: 48-53 - 2008
- [j1]Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien:
Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1141-1150 (2008) - [c3]Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien:
Robust analog neural network based on continuous valued number system. ISCAS 2008: 1384-1387 - 2007
- [c2]Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien:
Digital Multiplication using Continuous Valued Digits. ISCAS 2007: 3263-3266 - 2003
- [c1]Mitra Mirhassani, Majid Ahmadi, William C. Miller:
A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays. VLSI 2003: 339-344
Coauthor Index
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