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ORCIDMohammed A. S. Khalid
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2020 – today
- 2024
[j21]Madhan Thirumoorthi
, Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid:
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1423-1435 (2024)- [c24]Mahdi Hashemi, Mohammed A. S. Khalid, Roche Christopher:
SYCL-based Acceleration of Canny Edge Detector Algorithm Using DPC++. MWSCAS 2024: 258-262 - [c23]Sai Preetham Bonagiri, Mohammed A. S. Khalid:
New Resource Efficient Multi-PUF Techniques. MWSCAS 2024: 469-473 - 2023
- [j20]Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mohammed A. S. Khalid, Mitra Mirhassani:
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1509-1522 (2023) - 2022
- [j19]Madhan Thirumoorthi, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid:
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 603-614 (2022) - [c22]Shawn Smith, Mohammed A. S. Khalid:
Automated Generation and Integration of AUTOSAR RTE Configurations. CCECE 2022: 141-144 - 2021
- [j18]Asmeen Kashif, Mohammed A. S. Khalid:
Latency-optimised 3D multi-FPGA system with serial optical interface. Int. J. Comput. Aided Eng. Technol. 14(4): 556-574 (2021) - [j17]Madhan Thirumoorthi, Marko Jovanovic, Mitra Mirhassani, Mohammed A. S. Khalid:
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1912-1921 (2021) - 2020
- [j16]Weiying Zeng, Mohammed A. S. Khalid, Xiaoye Han, Jimi Tjong:
A Study on Extreme Learning Machine for Gasoline Engine Torque Prediction. IEEE Access 8: 104762-104774 (2020) - [j15]Asmeen Kashif, Mohammed A. S. Khalid:
Experimental evaluation and comparison of latency-optimized opticaland conventional multi-FPGA systems. Des. Autom. Embed. Syst. 24(2): 63-77 (2020) - [c21]Siddhant Luthra, Mohammed A. S. Khalid, Mohammad Abdul Moin Oninda:
FPGA-Based Evaluation and Implementation of an Automotive RADAR Signal Processing System using High-Level Synthesis. CCECE 2020: 1-6
2010 – 2019
- 2019
- [c20]Mohammad Abdul Momen, Mohammed A. S. Khalid, Mohammad Abdul Moin Oninda:
FPGA-Based Acceleration of Expectation Maximization Algorithm Using High-Level Synthesis. DASIP 2019: 41-46 - 2018
- [j14]Sabrina Zereen, Sundeep Lal, Mohammed A. S. Khalid, Sazzadur Chowdhury:
An FPGA-based controller for a 77 GHz MEMS tri-mode automotive radar. Microprocess. Microsystems 58: 34-40 (2018) - [c19]Liyuan Liu, Mohammed A. S. Khalid:
Acceleration of k-Nearest Neighbor Algorithm on FPGA using Intel SDK for OpenCL. MWSCAS 2018: 1070-1073 - 2017
- [j13]Jenita Priya Rajamanickam Manokaran, Mohammed A. S. Khalid:
Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs. Microprocess. Microsystems 51: 134-141 (2017) - [c18]Salem Alsaid, Esam Abdel-Raheem, Mohammed A. S. Khalid, Khaled Mayyas:
Variable tap-length algorithm using lattice structured LMS adaptive filters. CCECE 2017: 1-5 - 2016
- [j12]Weiying Zeng, Mohammed A. S. Khalid, Sazzadur Chowdhury:
In-Vehicle Networks Outlook: Achievements and Challenges. IEEE Commun. Surv. Tutorials 18(3): 1552-1571 (2016) - [j11]Qing Y. Tang, Mohammed A. S. Khalid:
Acceleration of k-Means Algorithm Using Altera SDK for OpenCL. ACM Trans. Reconfigurable Technol. Syst. 10(1): 6:1-6:19 (2016) - [c17]Sabrina Zereen, Sundeep Lal, Mohammed A. S. Khalid, Sazzadur Chowdhury:
An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar (Abstract Only). FPGA 2016: 278 - [c16]Ian Janik, Mohammed A. S. Khalid:
Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL. MWSCAS 2016: 1-4 - [c15]Asmeen Kashif, Mohammed A. S. Khalid:
Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures. MWSCAS 2016: 1-4 - 2015
- [c14]Ian Janik, Qing Y. Tang, Mohammed A. S. Khalid:
An overview of Altera SDK for OpenCL: A user perspective. CCECE 2015: 559-564 - [c13]Weiying Zeng, Mohammed A. S. Khalid, Sazzadur Chowdhury:
A qualitative comparison of FlexRay and Ethernet in vehicle networks. CCECE 2015: 571-576 - 2014
- [j10]Mike Brugge, Mohammed A. S. Khalid:
A Parameterizable NoC Router for FPGAs. J. Comput. 9(3): 519-528 (2014) - [c12]Raymond Lee, Mohammed A. S. Khalid, Esam Abdel-Raheem:
Configurable hardware implementation of a pipelined DNLMS adaptive filter. ICM 2014: 9-12 - [c11]Brajendra Kumar Singh, Kemal E. Tepe, Mohammed A. S. Khalid:
Control Mechanism to Solve False Blocking Problem at MAC Layer in Wireless Sensor Networks. VLSID 2014: 288-293 - 2013
- [j9]Junsong Liao, Brajendra Kumar Singh, Mohammed A. S. Khalid, Kemal E. Tepe:
FPGA based wireless sensor node with customizable event-driven architecture. EURASIP J. Embed. Syst. 2013: 5 (2013) - [c10]Abdelrazag Imbewa, Mohammed A. S. Khalid:
FLNR: A fast light-weight NoC router for FPGAs. MWSCAS 2013: 445-448 - 2011
- [c9]Krishnamohan Thangarajah, Behnam Shahrrava, Mohammed A. S. Khalid:
A novel simplified Log-MAP algorithm suitable for hardware implementation of turbo decoding. CCECE 2011: 1463-1465 - 2010
- [c8]Mike Brugge, Mohammed A. S. Khalid:
Design and evaluation of a parameterizable NoC router for FPGAs (abstract only). FPGA 2010: 292 - [i1]Linlin Zhang, Virginie Fresse, Mohammed A. S. Khalid, Dominique Houzet, Anne-Claire Legrand:
Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications. CoRR abs/1002.1881 (2010)
2000 – 2009
- 2009
- [j8]Linlin Zhang, Virginie Fresse, Mohammed A. S. Khalid, Dominique Houzet, Anne-Claire Legrand:
Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications. EURASIP J. Embed. Syst. 2009 (2009) - [j7]Ian D. L. Anderson, Mohammed A. S. Khalid:
SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays. IET Comput. Digit. Tech. 3(1): 24-32 (2009) - [c7]Omar A. Al Rayahi, Mohammed A. S. Khalid:
UWindsor Nios II: A soft-core processor for design space exploration. EIT 2009: 451-457 - [c6]Linlin Zhang, Virginie Fresse, Anne-Claire Legrand, Mohammed A. S. Khalid:
GALS NoC architectures on FPGA dedicated to multispectral image applications. EUSIPCO 2009: 978-982 - 2008
- [j6]Jason G. Tong, Mohammed A. S. Khalid:
Profiling Tools for FPGA-Based Embedded Systems: Survey and Quantitative Comparison. J. Comput. 3(6): 1-14 (2008) - [j5]Mohammed A. S. Khalid, Yonghong Xu:
A Fast and Effective Timing-Driven Placement Tool for FPGAS. J. Circuits Syst. Comput. 17(4): 663-673 (2008) - 2007
- [j4]Kevin Banovic, Mohammed A. S. Khalid, Esam Abdel-Raheem:
A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators. Digit. Signal Process. 17(6): 1071-1088 (2007) - 2006
- [j3]Raymond Lee, Esam Abdel-Raheem, Mohammed A. S. Khalid:
Computationally-Efficient DNLMS-Based Adaptive Algorithms for Echo Cancellation Application. J. Commun. 1(7): 1-8 (2006) - [j2]Kevin Banovic, Esam Abdel-Raheem, Mohammed A. S. Khalid:
A novel radius-adjusted approach for blind adaptive equalization. IEEE Signal Process. Lett. 13(1): 37-40 (2006) - [c5]Ian D. L. Anderson, Mohammed A. S. Khalid:
Design Space Exploration using Parameterized Cores: A Case Study. CCECE 2006: 1893-1896 - 2005
- [c4]Yonghong Xu, Mohammed A. S. Khalid:
QPF: Efficient Quadratic Placement for FPGAs. FPL 2005: 555-558 - [c3]Kevin Banovic, Esam Abdel-Raheem, Mohammed A. S. Khalid:
Hybrid Methods for Blind Adaptive Equalization: New Results and Comparisons. ISCC 2005: 275-280 - 2000
- [j1]Mohammed A. S. Khalid, Jonathan Rose:
A novel and efficient routing architecture for multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 30-39 (2000)
1990 – 1999
- 1999
- [c2]Mohammed A. S. Khalid, Jonathan Rose:
Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems. IPPS/SPDP Workshops 1999: 597-605 - 1998
- [c1]Mohammed A. S. Khalid, Jonathan Rose:
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. FPGA 1998: 45-54
Coauthor Index
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