"An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC ..."

Qifeng Huang et al. (2024)

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DOI: 10.1109/TVLSI.2024.3417015

access: closed

type: Journal Article

metadata version: 2024-10-22

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Qifeng Huang, Siji Huang, Yanhang Chen, Yifei Fan, Jie Yuan:
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1841-1851 (2024)

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