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2020 – today
- 2024
[j18]Jian-Wei Su
, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2304-2308 (2024)- [j17]Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong:
A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 848-859 (2024) - 2023
- [c21]Yi Chiu, Fang-Wei Tsai, Liang-Kai Wang, Yuan-Chieh Lee, Manu Garg, Hao-Chiao Hong:
CMOS MEMS Resonator for Physical Reservoir Computing. SENSORS 2023: 1-4 - [c20]Hao-Chiao Hong, Chien-Hung Chen, Yu-Wun Chen:
Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS. ITC-Asia 2023: 1-5 - 2022
- [j16]Long-Yi Lin, Hao-Chiao Hong:
Accurate and Fast On-Wafer Test Circuitry Integrated With a 140-dB-Input-Range Current Digitizer for Parameter Tests in WAT. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 114-127 (2022) - 2020
- [j15]Hao-Chiao Hong, Chih-Ko Yang:
Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems. IEEE Trans. Circuits Syst. 67-I(12): 4946-4959 (2020)
2010 – 2019
- 2019
- [j14]Hao-Chiao Hong, Long-Yi Lin, Yi Chiu:
Design of a 0.20-0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1840-1852 (2019) - [j13]Hao-Chiao Hong, Long-Yi Lin:
Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3467-3479 (2019) - [c19]Yi Chiu, You-Zen Chen, Chia-Chun Hsieh, Hao-Chiao Hong:
A Wireless Gauge Pressure Sensor with Enhanced Sensitivity Fabricated by Flexible PCB Technology For Intracranial Pressure Sensing. IEEE SENSORS 2019: 1-4 - [c18]Kun-Chih Wu, Meng-Shuan Wu, Hao-Chiao Hong:
Multiple Correlation Estimation Based Digital Background Calibration Scheme for Pipelined ADCs. ISCAS 2019: 1-5 - 2018
- [c17]Hao-Chiao Hong, Yi Chiu:
A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications. ISCAS 2018: 1-4 - [c16]Meng-Shuan Wu, Hao-Chiao Hong:
A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation. ISCAS 2018: 1-5 - 2017
- [c15]Pok Man Preston Law, Cheng-Wen Wu, Long-Yi Lin, Hao-Chiao Hong:
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages. ATS 2017: 5-10 - 2016
- [c14]Hao-Chiao Hong, Long-Yi Lin:
A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits. ATS 2016: 92-95 - [c13]Hong-Yi Huang, Kun-Yuan Chen, Jia-Hao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng:
Gm-C filter with automatic calibration scheme. DDECS 2016: 206-209 - [c12]Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng:
Low-voltage indoor energy harvesting using photovoltaic cell. DDECS 2016: 223-226 - 2014
- [j12]Shao-Feng Hung, Hao-Chiao Hong:
A Fully Integrated BIST \(\Delta \Sigma \) ADC Using the In-Phase and Quadrature Waves Fitting Procedure. IEEE Trans. Instrum. Meas. 63(12): 2750-2760 (2014) - [j11]Hao-Chiao Hong, Yung-Shun Chen, Wei-Chieh Fang:
14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1238-1247 (2014) - [c11]Shao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong:
A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles. ATS 2014: 63-67 - [c10]Yi-Wei Chen, Hao-Chiao Hong:
A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems. ISCAS 2014: 1134-1137 - [c9]Rong-Zhou Kuo, Hao-Chiao Hong:
A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits. VLSI-DAT 2014: 1-4 - 2013
- [c8]Long-Yi Lin, Hao-Chiao Hong:
Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model. Asian Test Symposium 2013: 62-66 - 2012
- [j10]Shao-Feng Hung, Hao-Chiao Hong:
Experimental Results of Testing a BIST Σ-Δ ADC on the HOY Wireless Test Platform. J. Electron. Test. 28(5): 571-584 (2012) - [j9]Hao-Chiao Hong:
A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 597-609 (2012) - [c7]Shao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong:
Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure. ISOCC 2012: 179-184 - 2011
- [j8]Sheng-Chuan Liang, Hao-Chiao Hong:
A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 503-507 (2011) - 2010
- [j7]Hao-Chiao Hong, Fang-Yi Su, Shao-Feng Hung:
A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure. IEEE Trans. Instrum. Meas. 59(9): 2334-2344 (2010)
2000 – 2009
- 2009
- [j6]Hao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song:
A Built-in-Self-Test Sigma-Delta ADC Prototype. J. Electron. Test. 25(2-3): 145-156 (2009) - [j5]Hao-Chiao Hong, Sheng-Chuan Liang:
A Decorrelating Design-for-Digital-Testability Scheme for Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 60-73 (2009) - [c6]Shao-Feng Hung, Hao-Chiao Hong, Sheng-Chuan Liang:
A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method. Asian Test Symposium 2009: 385-388 - 2008
- [c5]Hao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song:
A Cost Effective BIST Second-Order Sigma-Delta-Modulator. DDECS 2008: 314-319 - 2007
- [j4]Hao-Chiao Hong:
A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators. J. Electron. Test. 23(6): 527-538 (2007) - [j3]Hao-Chiao Hong, Guo-Ming Lee:
A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC. IEEE J. Solid State Circuits 42(10): 2161-2168 (2007) - [j2]Hao-Chiao Hong:
A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators. IEEE Trans. Very Large Scale Integr. Syst. 15(12): 1341-1350 (2007) - 2006
- [c4]Hao-Chiao Hong, Sheng-Chuan Liang:
A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems. ATS 2006: 255-264 - 2004
- [c3]Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng:
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. Asian Test Symposium 2004: 62-67 - [c2]Hao-Chiao Hong:
Design-for-digital-testability 30 MHz second-order Σ-Δ modulator. CICC 2004: 211-214 - 2003
- [j1]Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu, Ding-Ming Kwai:
Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. IEEE Trans. Circuits Syst. II Express Briefs 50(9): 553-566 (2003) - 2002
- [c1]Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu:
On-chip Analog Response Extraction with 1-Bit ? - Modulators. Asian Test Symposium 2002: 49-
Coauthor Index
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