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ORCIDMaolin Wang 0002
Person information
- affiliation: AI Chip Center for Emerging Smart Systems (ACCESS), Hong Kong
- affiliation (PhD 2020): University of Hong Kong, Department of Electrical and Electronic Engineering, Hong Kong
Other persons with the same name
- Maolin Wang (aka: Mao-Lin Wang) — disambiguation page
- Maolin Wang 0001
![[0000-0002-0073-0172]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-0073-0172")
— City University of Hong Kong, Department of Data Science, Hong Kong
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2020 – today
- 2024
[c9]Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang:
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. FPGA 2024: 143-153- [c8]Maolin Wang, Ian McInerney, Bartolomeo Stellato, Fengbin Tu, Stephen P. Boyd, Hayden Kwok-Hay So, Kwang-Ting Cheng:
Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming. MICRO 2024: 1574-1587 - 2023
- [c7]Yuhao Ding, Jiajun Wu, Yizhao Gao, Maolin Wang, Hayden Kwok-Hay So:
Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming. FCCM 2023: 83-93 - [c6]Maolin Wang, Ian McInerney, Bartolomeo Stellato, Stephen P. Boyd, Hayden Kwok-Hay So:
RSQP: Problem-specific Architectural Customization for Accelerated Convex Quadratic Optimization. ISCA 2023: 73:1-73:12 - 2022
- [j2]Maolin Wang, Kelvin C. M. Lee, Bob M. F. Chung, Sharatchandra Varma Bogaraju, Ho-Cheung Ng, Justin S. J. Wong, Ho Cheung Shum, Kevin K. Tsia, Hayden Kwok-Hay So:
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. 33(7): 2853-2866 (2022) - [j1]Maolin Wang, Seyedramin Rasoulinezhad, Philip H. W. Leong, Hayden Kwok-Hay So:
NITI: Training Integer Neural Networks Using Integer-Only Arithmetic. IEEE Trans. Parallel Distributed Syst. 33(11): 3249-3261 (2022) - 2020
- [i1]Maolin Wang, Seyedramin Rasoulinezhad, Philip H. W. Leong, Hayden Kwok-Hay So:
NITI: Training Integer Neural Networks Using Integer-only Arithmetic. CoRR abs/2009.13108 (2020)
2010 – 2019
- 2017
- [c5]Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So:
A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. FCCM 2017: 84 - [c4]Justin S. J. Wong, Runbin Shi, Maolin Wang, Hayden Kwok-Hay So:
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory. FPT 2017: 56-63 - 2016
- [c3]Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So:
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT 2016: 261-264 - [c2]Sam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So:
Towards FPGA-assisted spark: An SVM training acceleration case study. ReConFig 2016: 1-6 - [c1]Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So:
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig 2016: 1-6
Coauthor Index
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