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ORCIDManish Kumar Jaiswal
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2010 – 2019
- 2019
[j13]Manish Kumar Jaiswal
, Hayden Kwok-Hay So:
PACoGen: A Hardware Posit Arithmetic Core Generator. IEEE Access 7: 74586-74601 (2019)- [j12]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Design of quadruple precision multiplier architectures with SIMD single and double precision support. Integr. 65: 163-174 (2019) - 2018
- [j11]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division. Circuits Syst. Signal Process. 37(1): 383-407 (2018) - [j10]Farkhanda Syed, Zahid Ullah, Manish Kumar Jaiswal:
Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA. IEEE Embed. Syst. Lett. 10(3): 73-76 (2018) - [c17]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Universal number posit arithmetic generator on FPGA. DATE 2018: 1159-1162 - [c16]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Architecture Generator for Type-3 Unum Posit Adder/Subtractor. ISCAS 2018: 1-5 - 2017
- [j9]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 386-398 (2017) - 2016
- [c15]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Architecture for quadruple precision floating point division with multi-precision support. ASAP 2016: 239-240 - [c14]Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So:
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT 2016: 261-264 - [c13]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Taylor Series Based Architecture for Quadruple Precision Floating Point Division. ISVLSI 2016: 518-523 - [c12]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Dual-mode double precision division architecture. MWSCAS 2016: 1-4 - [c11]Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So:
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig 2016: 1-6 - 2015
- [j8]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung:
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2079-2090 (2015) - [j7]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung:
Z-TCAM: An SRAM-based Architecture for TCAM. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 402-406 (2015) - [c10]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So:
Architecture for Dual-Mode Quadruple Precision Floating Point Adder. ISVLSI 2015: 249-254 - [c9]Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Dual-mode double precision / two-parallel single precision floating point multiplier architecture. VLSI-SoC 2015: 213-218 - 2014
- [j6]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung:
E-TCAM: An Efficient SRAM-Based Architecture for TCAM. Circuits Syst. Signal Process. 33(10): 3123-3144 (2014) - [j5]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. 33(11): 3499-3526 (2014) - [j4]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 521-525 (2014) - [c8]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI 2014: 332-337 - 2013
- [j3]Manish Kumar Jaiswal, Ray C. C. Cheung:
VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique. Circuits Syst. Signal Process. 32(1): 15-27 (2013) - [j2]Manish Kumar Jaiswal, Ray C. C. Cheung:
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectron. J. 44(5): 421-430 (2013) - [c7]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung:
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM). FPL 2013: 1-4 - 2012
- [j1]Manish Kumar Jaiswal, Nitin Chandrachoodan:
FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture. IEEE Trans. Computers 61(1): 60-72 (2012) - [c6]Manish Kumar Jaiswal, Ray C. C. Cheung:
High Performance Reconfigurable Architecture for Double Precision Floating Point Division. ARC 2012: 302-313 - [c5]Manish Kumar Jaiswal, Ray C. C. Cheung:
Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers. FCCM 2012: 25-28 - [c4]Manish Kumar Jaiswal, Ray C. C. Cheung:
Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier. IPDPS Workshops 2012: 376-382 - [c3]Zahid Ullah, Manish Kumar Jaiswal, Y. C. Chan, Ray C. C. Cheung:
FPGA Implementation of SRAM-based Ternary Content Addressable Memory. IPDPS Workshops 2012: 383-389
2000 – 2009
- 2009
- [c2]Manish Kumar Jaiswal, Nitin Chandrachoodan:
Efficient Implementation of Floating-Point Reciprocator on FPGA. VLSI Design 2009: 267-271 - 2008
- [c1]Manish Kumar Jaiswal, Nitin Chandrachoodan:
Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA. ICIIS 2008: 1-4
Coauthor Index
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