"Analytical Delay Model for CPU-FPGA Data Paths in Programmable ..."

Mohammad Tahghighi, Sharad Sinha, Wei Zhang (2016)

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DOI: 10.1007/978-3-319-30481-6_13

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-02

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Mohammad Tahghighi, Sharad Sinha, Wei Zhang:
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. ARC 2016: 159-170

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