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ORCIDMatheus A. Cavalcante
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2020 – today
- 2024
[j10]Matteo Perotti
, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini:
Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor. IEEE Trans. Computers 73(7): 1822-1836 (2024)- [j9]Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim:
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 1957-1970 (2024) - [c18]Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini:
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. ASAP 2024: 172-173 - [c17]Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini:
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. DATE 2024: 1-6 - [c16]Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini:
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. ACM Great Lakes Symposium on VLSI 2024: 86-91 - [c15]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [i19]Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini:
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. CoRR abs/2401.04012 (2024) - [i18]Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini:
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. CoRR abs/2405.04988 (2024) - [i17]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR abs/2406.15068 (2024) - [i16]Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini:
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. CoRR abs/2407.05447 (2024) - 2023
- [b1]Matheus A. Cavalcante:
Fighting back the von Neumann bottleneck with small- and large-scale vector microprocessors. ETH Zurich, Zürich, Switzerland, Hartung-Gorre Verlag 2023, ISBN 978-3-86628-801-0, pp. 1-188 - [j8]Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini:
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic. IEEE Des. Test 40(6): 7-17 (2023) - [j7]Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini:
MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory. IEEE Trans. Computers 72(12): 3561-3575 (2023) - [j6]Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini:
Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3732-3736 (2023) - [c14]Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
Sparse Hamming Graph: A Customizable Network-on-Chip Topology. DAC 2023: 1-6 - [c13]Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. DAC 2023: 1-6 - [c12]Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst:
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. DAC 2023: 1-6 - [c11]Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini:
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. DATE 2023: 1-2 - [c10]Samuel Riedel, Matheus A. Cavalcante, Manos Frouzakis, Domenic Wüthrich, Enis Mustafa, Arlind Billa, Luca Benini:
MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS. ICECS 2023: 1-4 - [c9]MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David:
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS 2023: 1-5 - [i15]MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David:
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR abs/2302.05996 (2023) - [i14]Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini:
MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory. CoRR abs/2303.17742 (2023) - [i13]Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini:
FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic. CoRR abs/2305.08562 (2023) - [i12]Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst:
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. CoRR abs/2308.00154 (2023) - [i11]Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. CoRR abs/2309.10137 (2023) - [i10]Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini:
Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor. CoRR abs/2311.07493 (2023) - 2022
- [j5]Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini:
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. IEEE Trans. Computers 71(8): 1794-1809 (2022) - [c8]Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini:
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ASAP 2022: 43-51 - [c7]Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini:
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. DATE 2022: 394-399 - [c6]Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. ICCAD 2022: 22:1-22:9 - [c5]Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim:
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. ISLPED 2022: 15:1-15:6 - [c4]Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini:
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. ISVLSI 2022: 44-49 - [i9]Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. CoRR abs/2207.07970 (2022) - [i8]Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini:
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. CoRR abs/2209.00889 (2022) - [i7]Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini:
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. CoRR abs/2210.08882 (2022) - [i6]Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
Sparse Hamming Graph: A Customizable Network-on-Chip Topology. CoRR abs/2211.13980 (2022) - [i5]Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. CoRR abs/2211.13989 (2022) - 2021
- [c3]Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini:
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. DATE 2021: 701-706 - [i4]Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini:
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. CoRR abs/2112.01168 (2021) - 2020
- [j4]Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini:
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 530-543 (2020) - [c2]Matheus A. Cavalcante, Andreas Kurth, Fabian Schuiki, Luca Benini:
Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems. CF 2020: 81-88 - [i3]Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini:
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. CoRR abs/2009.05334 (2020) - [i2]Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini:
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. CoRR abs/2012.02973 (2020)
2010 – 2019
- 2019
- [i1]Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini:
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. CoRR abs/1906.00478 (2019) - 2018
- [j3]Matheus A. Cavalcante, Helder A. Pereira, Daniel A. R. Chaves, Raul C. Almeida Jr.:
Optimizing the cost function of power series routing algorithm for transparent elastic optical networks. Opt. Switch. Netw. 29: 57-64 (2018) - [j2]Matheus A. Cavalcante, Helder A. Pereira, Daniel A. R. Chaves, Raul C. Almeida Jr.:
Evolutionary Multiobjective Strategy for Regenerator Placement in Elastic Optical Networks. IEEE Trans. Commun. 66(8): 3583-3596 (2018) - 2017
- [j1]Matheus A. Cavalcante, Helder A. Pereira, Raul C. Almeida Jr.:
SimEON: an open-source elastic optical network simulator for academic and industrial purposes. Photonic Netw. Commun. 34(2): 193-201 (2017) - 2016
- [c1]Daniel A. R. Chaves, Matheus A. Cavalcante, Helder A. Pereira, Raul C. Almeida:
A case study of regenerator placement and regenerator assignment in dynamic translucent elastic optical networks. ICTON 2016: 1-4
Coauthor Index
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last updated on 2024-10-18 20:27 CEST by the dblp team
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