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ORCIDPaolo Mantovani
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2020 – today
- 2024
[c22]Vignesh Suresh
, Bakshree Mishra, Ying Jing, Zeran Zhu, Naiyin Jin, Charles Block, Paolo Mantovani, Davide Giri, Joseph Zuckerman, Luca P. Carloni, Sarita V. Adve:
Mozart: Taming Taxes and Composing Accelerators with Shared-Memory. PACT 2024: 183-200- [c21]Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei:
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ISSCC 2024: 262-264 - 2023
- [j9]Gabriele Tombesi, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel dos Santos, Tianyu Jia, David Brooks, Gu-Yeon Wei, Luca P. Carloni:
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs. IEEE Des. Test 40(6): 64-75 (2023) - 2022
- [c20]Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy, John-David Wellman, Kevin Tien, Luca P. Carloni, Kenneth L. Shepard, David Brooks, Gu-Yeon Wei, Pradip Bose:
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. ESSCIRC 2022: 269-272 - [c19]Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. ICCAD 2022: 20:1-20:9 - [i5]Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni:
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP. CoRR abs/2206.01901 (2022) - 2021
- [j8]Davide Giri, Kuan-Lin Chiu, Guy Eichler, Paolo Mantovani, Luca P. Carloni:
Accelerator Integration for Open-Source SoC Design. IEEE Micro 41(4): 8-14 (2021) - [c18]Joseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca P. Carloni:
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs. MICRO 2021: 350-365 - [i4]Joseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca P. Carloni:
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs. CoRR abs/2109.06382 (2021) - 2020
- [c17]Paolo Mantovani, Robert Margelli, Davide Giri, Luca P. Carloni:
HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis. CICC 2020: 1-8 - [c16]Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni:
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning. DATE 2020: 1049-1054 - [c15]Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni:
Agile SoC Development with Open ESP : Invited Paper. ICCAD 2020: 96:1-96:9 - [i3]Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni:
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning. CoRR abs/2004.03640 (2020) - [i2]Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni:
Agile SoC Development with Open ESP. CoRR abs/2009.01178 (2020)
2010 – 2019
- 2019
- [c14]Davide Giri, Paolo Mantovani, Luca P. Carloni:
Runtime reconfigurable memory hierarchy in embedded scalable platforms. ASP-DAC 2019: 719-726 - [c13]Kshitij Bhardwaj, Paolo Mantovani, Luca P. Carloni, Steven M. Nowick:
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs. ISLPED 2019: 1-6 - [c12]Luca P. Carloni, Emilio G. Cota, Giuseppe Di Guglielmo, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca Piccolboni, Michele Petracca:
Teaching Heterogeneous Computing with System-Level Design Methods. WCAE@ISCA 2019: 4:1-4:8 - [i1]Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators. CoRR abs/1912.10823 (2019) - 2018
- [j7]Davide Giri, Paolo Mantovani, Luca P. Carloni:
Accelerators and Coherence: An SoC Perspective. IEEE Micro 38(6): 36-45 (2018) - [c11]Davide Giri, Paolo Mantovani, Luca P. Carloni:
NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators. NOCS 2018: 1:1-1:8 - 2017
- [b1]Paolo Mantovani:
Scalable System-on-Chip Design. Columbia University, USA, 2017 - [j6]Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 435-448 (2017) - [j5]Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators. ACM Trans. Embed. Comput. Syst. 16(5s): 150:1-150:22 (2017) - [c10]Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
Broadening the exploration of the accelerator design space in embedded scalable platforms. HPEC 2017: 1-7 - [c9]Young-Jin Yoon, Paolo Mantovani, Luca P. Carloni:
System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip. NOCS 2017: 9:1-9:6 - 2016
- [c8]Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
High-level synthesis of accelerators in embedded scalable platforms. ASP-DAC 2016: 204-211 - [c7]Paolo Mantovani, Emilio G. Cota, Christian Pilato, Giuseppe Di Guglielmo, Luca P. Carloni:
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip. CASES 2016: 3:1-3:10 - [c6]Christian Pilato, Qirui Xu, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
On the design of scalable and reusable accelerators for big data applications. Conf. Computing Frontiers 2016: 406-411 - [c5]Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato, Giuseppe Di Guglielmo, Kenneth L. Shepard, Luca P. Carloni:
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems. DAC 2016: 157:1-157:6 - [c4]Emilio G. Cota, Paolo Mantovani, Luca P. Carloni:
Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration. ICS 2016: 27:1-27:12 - 2015
- [j4]Mario R. Casu, Paolo Mantovani:
A synchronous latency-insensitive RISC for better than worst-case design. Integr. 48: 72-82 (2015) - [c3]Emilio G. Cota, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
An Analysis of Accelerator Coupling in Heterogeneous Architectures. DAC 2015: 202:1-202:6 - 2014
- [j3]Emilio G. Cota, Paolo Mantovani, Michele Petracca, Mario R. Casu, Luca P. Carloni:
Accelerator Memory Reuse in the Dark Silicon Era. IEEE Comput. Archit. Lett. 13(1): 9-12 (2014) - [c2]Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
System-level memory optimization for high-level synthesis of component-based SoCs. CODES+ISSS 2014: 18:1-18:10 - 2012
- [j2]Noah Sturcken, Michele Petracca, Steve B. Warren, Paolo Mantovani, Luca P. Carloni, Angel V. Peterchev, Kenneth L. Shepard:
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI. IEEE J. Solid State Circuits 47(8): 1935-1945 (2012) - 2011
- [c1]Mario R. Casu, Stefano Colazzo, Paolo Mantovani:
Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study. ACM Great Lakes Symposium on VLSI 2011: 163-168
1990 – 1999
- 1996
- [j1]Alessandro Avellone, Camillo Fiorentini, Paolo Mantovani, Pierangelo Miglioli:
On maximal intermediate predicate constructive logics. Stud Logica 57(2/3): 373-408 (1996)
Coauthor Index
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