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ORCIDMadhavan Manivannan
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2020 – today
- 2024
[c19]Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs:
SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs. IPDPS 2024: 325-336- 2023
- [j9]Muhammad Waqar Azhar
, Madhavan Manivannan, Per Stenström:
Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints. ACM Trans. Archit. Code Optim. 20(3): 44:1-44:25 (2023) - [c18]Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou:
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF 2023: 309-314 - [c17]Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström:
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. EuroS&P 2023: 631-650 - [c16]Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström:
SCALE: Secure and Scalable Cache Partitioning. HOST 2023: 68-79 - [c15]Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs:
JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. ICPP 2023: 828-838 - [i8]Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs:
JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. CoRR abs/2306.04615 (2023) - 2022
- [j8]Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström:
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications. ACM Trans. Archit. Code Optim. 19(2): 21:1-21:27 (2022) - [j7]Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, Miquel Pericàs:
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. ACM Trans. Archit. Code Optim. 19(2): 27:1-27:29 (2022) - [c14]Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, Miquel Pericàs:
STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures. SBAC-PAD 2022: 326-335 - [i7]Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, Miquel Pericàs:
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. CoRR abs/2201.12186 (2022) - [i6]Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström:
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. CoRR abs/2212.10221 (2022) - 2021
- [c13]Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs:
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. PACT 2021: 213-225 - [i5]Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs:
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. CoRR abs/2102.11528 (2021) - 2020
- [j6]Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström:
Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems. J. Parallel Distributed Comput. 144: 246-259 (2020) - [c12]Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck:
Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading. DAC 2020: 1-6 - [c11]Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, Seyed Saber Nabavi Larimi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber:
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. DATE 2020: 169-174 - [c10]Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck:
Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading. DATE 2020: 967-970 - [c9]Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar, Madhavan Manivannan, Miquel Pericàs:
Scheduling Task-parallel Applications in Dynamically Asymmetric Environments. ICPP Workshops 2020: 18:1-18:10 - [c8]Nadja Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs:
DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors. IPDPS 2020: 578-589 - [c7]Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström:
Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. IPDPS 2020: 590-601 - [i4]Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar, Madhavan Manivannan, Miquel Pericàs:
Scheduling Task-parallel Applications in Dynamically Asymmetric Environments. CoRR abs/2009.00915 (2020)
2010 – 2019
- 2019
- [i3]Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström:
Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems. CoRR abs/1911.05101 (2019) - [i2]Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström:
Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. CoRR abs/1911.05114 (2019) - [i1]Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Daniel Ödman, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Th. Jungeblu, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber:
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. CoRR abs/1912.01563 (2019) - 2018
- [j5]Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström:
Global Dead-Block Management for Task-Parallel Programs. ACM Trans. Archit. Code Optim. 15(3): 33:1-33:25 (2018) - 2017
- [j4]Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström:
Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. 16(2): 145-148 (2017) - 2016
- [b1]Madhavan Manivannan:
Towards Runtime-Assisted Cache Management for Task-Parallel Programs. Chalmers University of Technology, Gothenburg, Sweden, 2016 - [c6]Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström:
RADAR: Runtime-assisted dead region management for last-level caches. HPCA 2016: 644-656 - 2014
- [c5]Madhavan Manivannan, Per Stenström:
Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures. IPDPS 2014: 625-636 - 2013
- [c4]Madhavan Manivannan, Anurag Negi, Per Stenström:
Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. ICPP 2013: 517-522 - 2011
- [c3]Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström:
Implications of Merging Phases on Scalability of Multi-core Architectures. ICPP 2011: 622-631 - [c2]Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström:
Poster: implications of merging phases on scalability of multi-core architectures. ICS 2011: 380
2000 – 2009
- 2009
- [j3]Nagarajan Venkateswaran, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan, T. P. Ramnath Sai Sagar, Madhavan Manivannan, Sriram Murali, Vinoth Krishnan Elangovan:
Towards modeling and integrated design automation of supercomputing clusters (MIDAS). Comput. Sci. Res. Dev. 24(1-2): 1-10 (2009) - 2008
- [c1]Nagarajan Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, T. R. S. Sagar, S. Aananthakrishanan, S. Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishnamurthy, Karthik Chandrasekar, Viswanath Venkatesan, Balaji Subramaniam, V. Sangkar, Aravind Vasudevan, Shrikanth Ganapathy, Sriram Murali, M. Thyagarajan:
On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. IPDPS 2008: 1-8 - 2007
- [j2]Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Karthik Chandrasekar, Prem Kumar Ramesh, Viswanath Venkatesan, Arvindakshan Babu, Sudharshan:
Future generation supercomputers I: a paradigm for node architecture. SIGARCH Comput. Archit. News 35(5): 49-60 (2007) - [j1]Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krishnamurthy, Sivaramakrishnan:
Future generation supercomputers II: a paradigm for cluster architecture. SIGARCH Comput. Archit. News 35(5): 61-70 (2007)
Coauthor Index
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