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ORCIDVassilis Papaefstathiou
Vassilios Papaefstathiou – Vassilis D. Papaefstathiou
Person information
- affiliation: University of Crete, Department of Computer Science, Heraklion, Greece
- affiliation: Foundation for Research & Technology - Hellas (FORTH), Heraklion, Greece
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2020 – today
- 2024
[c36]Michalis Gianioudis
, Pantelis Xirouchakis, Charisios Loukas, Evangelos Mageiropoulos, Orestis Mousouros, Sokratis Mpartzis, Aggelos Ioannou, Vassilis Papaefstathiou, Manolis Katevenis, Nikolaos Chrysos:
Low-latency Communication in RISC-V Clusters. HPC Asia 2024: 73-83- 2023
- [c35]Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou:
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF 2023: 309-314 - [c34]Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani:
Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V. SC Workshops 2023: 1543-1549 - [c33]Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta:
Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study. ISC Workshops 2023: 526-537 - [i6]Filippo Mantovani, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Giorgos Ieronymakis, Nikos Dimou, Vassilis Papaefstathiou, Jesús Labarta:
Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study. CoRR abs/2306.01797 (2023) - [i5]Manolis Ploumidis, Fabien Chaix, Nikolaos Chrysos, Marios Asiminakis, Vassilis Flouris, Nikolaos D. Kallimanis, Nikolaos Kossifidis, Michael Nikoloudakis, Polydoros Petrakis, Nikolaos Dimou, Michalis Gianioudis, Georgios Ieronymakis, Aggelos Ioannou, George Kalokerinos, Pantelis Xirouchakis, Georgios Ailamakis, Astrinos Damianakis, Michael Ligerakis, Ioannis Makris, Theocharis Vavouris, Manolis Katevenis, Vassilis Papaefstathiou, Manolis Marazakis, Iakovos Mavroidis:
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack. CoRR abs/2307.09371 (2023) - [i4]Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani:
Short reasons for long vectors in HPC CPUs: a study based on RISC-V. CoRR abs/2309.06865 (2023) - 2022
- [j15]Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Gianioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, Manolis Katevenis:
Optimized Page Fault Handling During RDMA. IEEE Trans. Parallel Distributed Syst. 33(10): 3990-4005 (2022) - 2021
- [j14]Ahsen Ejaz, Vassilis Papaefstathiou, Ioannis Sourdis:
HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers. IEEE/ACM Trans. Netw. 29(1): 318-331 (2021) - [c32]Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau:
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS 2021: 18-29 - 2020
- [j13]David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti, Giuliano Taffoni:
Performance and Energy Footprint Assessment of FPGAs and GPUs on HPC Systems Using Astrophysics Application. Comput. 8(2): 34 (2020) - [j12]George Christou, Giorgos Vasiliadis, Vassilis Papaefstathiou, Antonis Papadogiannakis, Sotiris Ioannidis:
On Architectural Support for Instruction Set Randomization. ACM Trans. Archit. Code Optim. 17(4): 36:1-36:26 (2020) - [j11]Aggelos D. Ioannou, Konstantinos Georgopoulos, Pavlos Malakonakis, Dionisios N. Pnevmatikatos, Vassilis D. Papaefstathiou, Ioannis Papaefstathiou, Iakovos Mavroidis:
UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 13(4): 21:1-21:32 (2020) - [c31]Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis:
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems. HPCA 2020: 649-662 - [c30]Antonis Psistakis, Nikos Chrysos, Fabien Chaix, Marios Asiminakis, Michalis Giannioudis, Pantelis Xirouchakis, Vassilis Papaefstathiou, Manolis Katevenis:
PART: Pinning Avoidance in RDMA Technologies. NOCS 2020: 1-8 - [i3]David Goz, Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Giuliano Taffoni, Francesco Simula, Antonio Ragagnin, Luca Tornatore, Igor Coretti:
Performance and energy footprint assessment of FPGAs and GPUs on HPC systems using Astrophysics application. CoRR abs/2003.03283 (2020) - [i2]Miquel Pericàs, Oscar Palomar, Vassilis Papaefstathiou, Mahmoud Eljammaly:
Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020). CoRR abs/2005.07619 (2020)
2010 – 2019
- 2019
- [j10]Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis:
Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache. ACM Trans. Archit. Code Optim. 15(4): 65:1-65:23 (2019) - [j9]George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Xiaojun Yang, Dionisios N. Pnevmatikatos, Manolis Katevenis:
Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. Trans. High Perform. Embed. Archit. Compil. 5: 100-120 (2019) - [c29]Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis:
LLC-Guided Data Migration in Hybrid Memory Systems. IPDPS 2019: 932-942 - [c28]Georgios Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, Igor Coretti:
Direct N-Body Application on Low-Power and Energy-Efficient Parallel Architectures. PARCO 2019: 583-592 - [c27]Fabien Chaix, Georgios Ailamakis, Theocharis Vavouris, Astrinos Damianakis, Manolis Katevenis, Iakovos Mavroidis, Aggelos Ioannou, Nikolaos Kossifidis, Nikolaos Dimou, Giorgos Ieronymakis, Manolis Marazakis, Vassilis Papaefstathiou, Vassilis Flouris, Mihailis Ligerakis:
Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping. H2RC@SC 2019: 34-41 - [c26]Manolis Ploumidis, Nikolaos D. Kallimanis, Marios Asiminakis, Nikos Chrysos, Pantelis Xirouchakis, Michalis Gianoudis, Leandros Tzanakis, Nikolaos Dimou, Antonis Psistakis, Panagiotis Peristerakis, Giorgos Kalokairinos, Vassilis Papaefstathiou, Manolis Katevenis:
Software and Hardware Co-design for Low-Power HPC Platforms. ISC Workshops 2019: 88-100 - [i1]David Goz, Giorgos Ieronymakis, Vassilis Papaefstathiou, Nikolaos Dimou, Sara Bertocco, Antonio Ragagnin, Luca Tornatore, Giuliano Taffoni, Igor Coretti:
Direct N-body application on low-power and energy-efficient parallel architectures. CoRR abs/1910.14496 (2019) - 2018
- [j8]Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis:
DDRNoC: Dual Data-Rate Network-on-Chip. ACM Trans. Archit. Code Optim. 15(2): 25:1-25:24 (2018) - [j7]Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström:
Global Dead-Block Management for Task-Parallel Programs. ACM Trans. Archit. Code Optim. 15(3): 33:1-33:25 (2018) - [c25]Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis:
FusionCache: Using LLC tags for DRAM cache. DATE 2018: 593-596 - [c24]Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström:
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness. HPCA 2018: 143-155 - [c23]Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis:
FreewayNoC: A DDR NoC with Pipeline Bypassing. NOCS 2018: 8:1-8:8 - 2017
- [j6]Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström:
Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. 16(2): 145-148 (2017) - [j5]Muhammad Waqar Azhar, Per Stenström, Vassilis Papaefstathiou:
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures. ACM Trans. Archit. Code Optim. 14(4): 41:1-41:25 (2017) - [c22]Alirad Malek, Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis:
Odd-ECC: on-demand DRAM error correcting codes. MEMSYS 2017: 96-111 - [c21]Evangelos Vasilakis, Ioannis Sourdis, Vassilis Papaefstathiou, Antonis Psathakis, Manolis G. H. Katevenis:
Modeling energy-performance tradeoffs in ARM big.LITTLE architectures. PATMOS 2017: 1-8 - 2016
- [c20]Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino:
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems. DATE 2016: 696-701 - [c19]Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström:
RADAR: Runtime-assisted dead region management for last-level caches. HPCA 2016: 644-656 - [c18]Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström:
Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories. MEMSYS 2016: 121-132 - 2015
- [c17]Antonis Psathakis, Vassilis Papaefstathiou, Nikolaos Chrysos, Fabien Chaix, Evangelos Vasilakis, Dionisios N. Pnevmatikatos, Manolis Katevenis:
A Systematic Evaluation of Emerging Mesh-like CMP NoCs. ANCS 2015: 159-170 - 2014
- [b1]Vassilis Papaefstathiou:
Architectural support for software-guided energy reduction of manycore communication. University of Crete, Greece, 2014 - [j4]Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Iakovos Mavroidis, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos:
FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards. J. Syst. Archit. 60(6): 481-493 (2014) - [c16]Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos:
Design trade-offs in energy efficient NoC architectures. NOCS 2014: 186-187 - [c15]Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios N. Pnevmatikatos:
Design space exploration for fair resource-allocated NoC architectures. ICSAMOS 2014: 141-148 - 2013
- [j3]Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Stamatis G. Kavadias, Manolis Katevenis:
NP-SARC: Scalable network processing in the SARC multi-core FPGA platform. J. Syst. Archit. 59(1): 39-47 (2013) - [c14]Antonis Papadogiannakis, Laertis Loutsis, Vassilis Papaefstathiou, Sotiris Ioannidis:
ASIST: architectural support for instruction set randomization. CCS 2013: 981-992 - [c13]Vassilis Papaefstathiou, Manolis Katevenis, Dimitrios S. Nikolopoulos, Dionisios N. Pnevmatikatos:
Prefetching and cache management using task lifetimes. ICS 2013: 325-334 - 2012
- [c12]Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitrios Tsaliagkos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitrios S. Nikolopoulos:
Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures. FCCM 2012: 61-64 - 2011
- [c11]Pranav Tendulkar, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Dimitrios S. Nikolopoulos, Manolis Katevenis:
Fine-grain OpenMP runtime support with explicit communication hardware primitives. DATE 2011: 891-894 - 2010
- [j2]Manolis Katevenis, Vassilis Papaefstathiou, Stamatis G. Kavadias, Dionisios N. Pnevmatikatos, Federico Silla, Dimitrios S. Nikolopoulos:
Explicit Communication and Synchronization in SARC. IEEE Micro 30(5): 30-41 (2010) - [c10]Christoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis:
Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. ReConFig 2010: 328-333
2000 – 2009
- 2009
- [c9]George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Manolis Katevenis, Dionisios N. Pnevmatikatos, Xiaojun Yang:
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. ICSAMOS 2009: 149-156 - 2007
- [c8]Manolis Marazakis, Vassilis Papaefstathiou, Angelos Bilas:
Optimization and bottleneck analysis of network block I/O in commodity storage systems. ICS 2007: 33-42 - [c7]Ioannis Papaefstathiou, Vassilis Papaefstathiou:
Memory-Efficient 5D Packet Classification At 40 Gbps. INFOCOM 2007: 1370-1378 - [c6]Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis G. Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis:
Prototyping Efficient Interprocessor Communication Mechanisms. ICSAMOS 2007: 26-33 - 2006
- [c5]Manolis Marazakis, Vassilis Papaefstathiou, Giorgos Kalokairinos, Angelos Bilas:
Experiences from Debugging a PCIX-based RDMA-capable NIC. CLUSTER 2006 - [c4]Vassilis Papaefstathiou, Ioannis Papaefstathiou:
A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments. DATE Designers' Forum 2006: 112-117 - [c3]Ioannis Papaefstathiou, Vassilis Papaefstathiou:
An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks. ICC 2006: 211-216 - [c2]Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, Angelos Bilas:
Efficient remote block-level I/O over an RDMA-capable NIC. ICS 2006: 97-106 - 2005
- [c1]Vassilis Papaefstathiou, Ioannis Papaefstathiou:
A Memory Efficient, 100 Gb/sec MAC Classification Engine. LCN 2005: 470-471 - 2004
- [j1]Ioannis Papaefstathiou, Vassilis Papaefstathiou, Christos P. Sotiriou:
Design-space exploration of the most widely used cryptography algorithms. Microprocess. Microsystems 28(10): 561-571 (2004)
Coauthor Index
Giorgos Ieronymakis
aka: Georgios Ieronymakis
aka: Georgios Ieronymakis
Manolis Katevenis
aka: Manolis G. H. Katevenis
aka: Manolis G. H. Katevenis
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