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2020 – today
- 2022
[c5]Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang:
Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines. ISPD 2022: 13-20- 2020
- [c4]Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang:
Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization. DAC 2020: 1-2
2010 – 2019
- 2016
- [c3]Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, Ping Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, Chia-Hung Kao, Yi-Chang Chen, Chia-Lin Ho, Yenchieh Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng:
A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications. ESSCIRC 2016: 109-112 - 2015
- [j1]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 301-305 (2015) - [c2]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC 2015: 96-99 - 2014
- [c1]Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. ISCAS 2014: 409-412
Coauthor Index
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