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2020 – today
- 2022
[j17]Jung-San Lee, Ying-Chin Chen, Chit-Jie Chew, Chih-Lung Chen
, Thu-Nguyet Huynh, Chung-Wei Kuo:
CoNN-IDS: Intrusion detection system based on collaborative neural networks and agile training. Comput. Secur. 122: 102908 (2022)- 2021
- [j16]Chit-Jie Chew, Ying-Chin Chen, Jung-San Lee, Chih-Lung Chen, Kuo-Yu Tsai:
Preserving indomitable DDoS vitality through resurrection social hybrid botnet. Comput. Secur. 106: 102284 (2021) - [j15]Yong-Ru Lu, Shen-Iuan Liu, Yu-Che Yang, Han-Chang Kang, Chih-Lung Chen, Ka-Un Chan, Ying-Hsi Lin:
A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 873-877 (2021) - 2020
- [j14]Wei-Chih Hong, Ding-Ray Huang, Chih-Lung Chen, Jung-San Lee:
Towards Accurate and Efficient Classification of Power System Contingencies and Cyber-Attacks Using Recurrent Neural Networks. IEEE Access 8: 123297-123309 (2020)
2010 – 2019
- 2016
- [j13]Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 863-867 (2016) - [j12]Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang:
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1293-1304 (2016) - [c11]Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. A-SSCC 2016: 337-340 - 2015
- [j11]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 507-516 (2015) - [j10]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 301-305 (2015) - [j9]Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2523-2532 (2015) - [c10]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC 2015: 96-99 - [c9]Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee:
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. ISCAS 2015: 1450-1453 - 2014
- [c8]Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee:
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. A-SSCC 2014: 229-232 - [c7]Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. ISCAS 2014: 409-412 - [c6]Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee:
A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. VLSIC 2014: 1-2 - 2013
- [j8]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes. IEEE Commun. Lett. 17(5): 976-979 (2013) - [j7]Hsiu-Chi Chang, Chih-Lung Chen, Hsie-Chia Chang:
An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes. IEEE Commun. Lett. 17(10): 1980-1983 (2013) - [j6]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, John K. Zao, Hsie-Chia Chang:
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection. IEEE Trans. Multim. 15(8): 2162-2175 (2013) - [c5]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes. WCSP 2013: 1-6 - 2012
- [j5]Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. IEEE J. Solid State Circuits 47(4): 817-831 (2012) - [j4]Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 47(9): 2246-2257 (2012) - [c4]Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang:
Non-repetitive encoding with increased degree-1 encoding symbols for LT codes. APCCAS 2012: 655-658 - [c3]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Stochastic decoding for LDPC convolutional codes. ISCAS 2012: 2621-2624 - [c2]Kuo-Kuang Yen, Chih-Lung Chen, Hsie-Chia Chang:
An improved LT encoding scheme with extended chain lengths. ISITA 2012: 11-15 - 2010
- [j3]Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. IEEE J. Solid State Circuits 45(11): 2330-2340 (2010)
2000 – 2009
- 2009
- [j2]Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 734-738 (2009) - [c1]Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee:
A 11.5-Gbps LDPC decoder based on CP-PEG code construction. ESSCIRC 2009: 412-415 - 2008
- [j1]Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. IEEE J. Solid State Circuits 43(3): 684-694 (2008)
Coauthor Index
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