"A performance-driven circuit bipartitioning algorithm for multi-FPGA ..."

Masato Inagi et al. (2006)

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DOI: 10.1109/FPT.2006.270348

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-09

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Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. FPT 2006: 361-364

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