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ORCIDLogan Rakai
Person information
- affiliation: University of Calgary, Canada
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2020 – today
- 2022
[c18]Reza Hedayati Majdabadi, Mea Wang, Logan Rakai:
SODA-Stream: SDN Optimization for Enhancing QoE in DASH Streaming. NOMS 2022: 1-5- 2021
- [j13]Seyedehmehrnaz Mireslami
, Logan Rakai, Mea Wang, Behrouz Homayoun Far:
Dynamic Cloud Resource Allocation Considering Demand Uncertainty. IEEE Trans. Cloud Comput. 9(3): 981-994 (2021) - 2020
- [j12]Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat:
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1177-1190 (2020)
2010 – 2019
- 2018
- [j11]Diego F. G. Coelho, Vassil S. Dimitrov, Logan Rakai:
Efficient computation of tridiagonal matrices largest eigenvalue. J. Comput. Appl. Math. 330: 268-275 (2018) - [c17]Aysa Fakheri Tabrizi, Nima Karimpour Darav, Shuchang Xu, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat:
A machine learning framework to identify detailed routing short violations from a placed netlist. DAC 2018: 48:1-48:6 - 2017
- [j10]Amin Farshidi, Laleh Behjat, Logan M. Rakai, David T. Westwick:
A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 412-416 (2017) - [j9]Seyedehmehrnaz Mireslami, Logan Rakai, Behrouz Homayoun Far, Mea Wang:
Simultaneous Cost and QoS Optimization for Cloud Resource Allocation. IEEE Trans. Netw. Serv. Manag. 14(3): 676-689 (2017) - [c16]Vassil S. Dimitrov, Viduneth Ariyarathna, Diego F. G. Coelho, Logan Rakai, Arjuna Madanayake, Renato J. Cintra:
A Parallel Method for the Computation of Matrix Exponential Based on Truncated Neumann Series. ARITH 2017: 35-42 - [c15]Ali Farshidi, Logan Rakai, Laleh Behjat:
An efficient optimal clock network buffer sizing with slew consideration. CCECE 2017: 1-4 - [c14]Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Andrew A. Kennings, Laleh Behjat:
Detailed routing violation prediction during placement using machine learning. VLSI-DAT 2017: 1-4 - 2016
- [j8]Aysa Fakheri Tabrizi, Laleh Behjat, William Swartz, Logan M. Rakai:
A fast force-directed simulated annealing for 3D IC partitioning. Integr. 55: 202-211 (2016) - [c13]Payam Zamani Dehkordi, Logan Rakai, Hamidreza Zareipour, William D. Rosehart:
Big Data Analytics for Modelling the Impact of Wind Power Generation on Competitive Electricity Market Prices. HICSS 2016: 2528-2535 - 2015
- [c12]Seyedehmehrnaz Mireslami, Logan Rakai, Mea Wang, Behrouz Homayoun Far:
Minimizing Deployment Cost of Cloud-Based Web Application with Guaranteed QoS. GLOBECOM 2015: 1-6 - [c11]Payam Zamani Dehkordi, Logan Rakai, Hamidreza Zareipour:
A Data-Driven Method to Detect the Abnormal Instances in an Electricity Market. ICMLA 2015: 1050-1055 - [c10]Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan M. Rakai, Andrew A. Kennings, William Swartz, Laleh Behjat:
A Detailed Routing-Aware Detailed Placement Technique. ISVLSI 2015: 38-43 - [p1]Logan Rakai, Amin Farshidi:
Sizing Digital Circuits Using Convex Optimization Techniques. Computational Intelligence in Digital and Network Designs and Applications 2015: 3-32 - 2014
- [j7]Amin Farshidi, Logan M. Rakai, Laleh Behjat, David T. Westwick:
Optimal gate sizing using a self-tuning multi-objective framework. Integr. 47(3): 347-355 (2014) - [j6]Logan M. Rakai, Amin Farshidi, David T. Westwick, Laleh Behjat:
Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 532-545 (2014) - [c9]Logan M. Rakai, William D. Rosehart:
GPU-Accelerated Solutions to Optimal Power Flow Problems. HICSS 2014: 2511-2516 - 2013
- [j5]Amin Farshidi, Logan M. Rakai, Bardia Samimi, Laleh Behjat, David T. Westwick:
A new a priori net length estimation technique for integrated circuits using radial basis functions. Comput. Electr. Eng. 39(4): 1204-1218 (2013) - [c8]Amin Farshidi, Logan M. Rakai, Laleh Behjat, David T. Westwick:
A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications. ACM Great Lakes Symposium on VLSI 2013: 305-310 - [c7]Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick:
Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes. ISPD 2013: 154-161 - 2012
- [b1]Logan Rakai:
Methods for Solving Modern, Scale-Borne Problems in VLSI Physical Design. University of Calgary, Alberta, Canada, 2012 - [j4]Logan M. Rakai, Laleh Behjat, Sebastian Martin, Jose Aguado:
An algebraic multigrid-based algorithm for circuit clustering. Appl. Math. Comput. 218(9): 5202-5216 (2012) - [j3]Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick:
A New Length-Based Algebraic Multigrid Clustering Algorithm. VLSI Design 2012: 395260:1-395260:14 (2012) - [c6]Logan M. Rakai, Laleh Behjat:
Parallel clock tree synthesis. CCECE 2012: 1-4 - 2011
- [j2]Amin Farshidi, Laleh Behjat, Logan M. Rakai, Bahareh Fathi:
A pre-placement individual net length estimation model and an application for modern circuits. Integr. 44(2): 111-122 (2011) - [c5]Yang-Yang Li, Logan M. Rakai, Laleh Behjat, Bill Swartz:
Wirelength and congestion estimation for routability-driven placement. SLIP 2011: 1
2000 – 2009
- 2009
- [j1]Logan M. Rakai, Laleh Behjat, Shawki Areibi, Tamás Terlaky:
A Multilevel Congestion-Based Global Router. VLSI Design 2009: 537341:1-537341:13 (2009) - [c4]Bahareh Fathi, Laleh Behjat, Logan M. Rakai:
A pre-placement net length estimation technique for mixed-size circuits. SLIP 2009: 45-52 - 2007
- [c3]Jianhua Li, Laleh Behjat, Logan Rakai:
Clustering algorithms for circuit partitioning and placement problems. ECCTD 2007: 547-550 - [c2]Laleh Behjat, Jianhua Li, Logan M. Rakai, Jie Huang:
Two Clustering Preprocessing Techniques for Large-Scale Circuits. ISCAS 2007: 1057-1060 - 2006
- [c1]Logan M. Rakai, Jianhua Li, Laleh Behjat, Jie Huang:
A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits. SiPS 2006: 66-70
Coauthor Index
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