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ORCID17th ISQED 2016: Santa Clara, California, USA
- 17th International Symposium on Quality Electronic Design, ISQED 2016, Santa Clara, CA, USA, March 15-16, 2016. IEEE 2016, ISBN 978-1-5090-1213-8
- Brian Cline, Saibal Mukhopadhyay, Peter J. Wright, Hai Li, Vinod Viswanath, Paul Wesling, Gang Qu, Ali Iranmanesh:
Welcome.
Session 1A: Low Power Memory & Logic Design
- Seyed Alireza Pourbakhsh
, Xiaowei Chen, Dongliang Chen, Xin Wang, Na Gong, Jinhui Wang:
Sizing-priority based low-power embedded memory for mobile video applications. 1-5 - Navid Khoshavi, Xunchao Chen, Jun Wang, Ronald F. DeMara:
Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis. 6-11 - Harsh N. Patel, Farah B. Yahya, Benton H. Calhoun:
Optimizing SRAM bitcell reliability and energy for IoT applications. 12-17 - Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Variability- and correlation-aware logical effort for near-threshold circuit design. 18-23
Session 1B: Advanced Three-Dimensional Integrated Circuits
- M. Amimul Ehsan, Hongyu An, Zhen Zhou, Yang Yi:
Design challenges and methodologies in 3D integration for neuromorphic computing systems. 24-28 - Sheng-En David Lin, Partha Pratim Pande, Dae Hyun Kim:
Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs. 29-34 - Tiantao Lu, Zhiyuan Yang, Ankur Srivastava:
Electromigration-aware placement for 3D-ICs. 35-40 - Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Monolithic 3D IC design: Power, performance, and area impact at 7nm. 41-48
Session 2A: Network on a Chip
- Alireza Shafaei, Yanzhi Wang, Lizhong Chen, Shuang Chen, Massoud Pedram:
Maximizing the performance of NoC-based MPSoCs under total power and power density constraints. 49-56 - Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha:
Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures. 57-62 - Venkata Yaswanth Raparti, Sudeep Pasricha:
Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures. 63-68 - Noha Gamal, Hossam A. H. Fahmy, Yehea I. Ismail, Hassan Mostafa:
Design guidelines for embeded NoCs on FPGAs. 69-74 - Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A delay variation and floorplan aware high-level synthesis algorithm with body biasing. 75-80
Session 2C: Circuits and Architecture for Emerging Logic and Memory Technologies
- Hengyu Zhao, Hongbin Sun, Qiang Yang, Tai Min, Nanning Zheng:
Exploring the use of volatile STT-RAM for energy efficient video processing. 81-87 - Mohsen Imani, Shruti Patil, Tajana Simunic Rosing:
Low power data-aware STT-RAM based hybrid cache architecture. 88-94 - Jizhe Zhang, Sandeep K. Gupta:
Yield estimation and statistical design of memristor cross-point memory systems. 95-100 - Mohsen Imani, Pietro Mercati, Tajana Rosing:
ReMAM: Low energy Resistive Multi-stage Associative Memory for energy efficient computing. 101-106 - Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications. 107-112
Session 3A: On-Chip Machine Learning and Neuromorphic Computing
- Luca Bochi Saldanha, Christophe Bobda:
Sparsely connected neural networks in FPGA for handwritten digit recognition. 113-117 - Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong:
Neuromorphic architectures with electronic synapses. 118-123 - Dan Christiani, Cory E. Merkel, Dhireesha Kudithipudi:
Invited: Towards a scalable neuromorphic hardware for classification and prediction with stochastic No-Prop algorithms. 124-128
Session P: Poster Presentations
- Jian Hu, Tun Li, Sikun Li:
Equivalence checking between SLM and RTL using machine learning techniques. 129-134 - Peter Sarson:
Very low supply voltage room temperature test to screen low temperature soft blown fuse fails which result in a resistive bridge. 135-139 - Ming Fan, Rong Rong, Xinwei Niu:
On-line harmonic-aware partitioned scheduling for real-time multi-core systems under RMS. 140-145 - Eman El Mandouh, Amr G. Wassal:
Covgen: A framework for automatic extraction of functional coverage models. 146-151 - Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
In-situ Trojan authentication for invalidating hardware-Trojan functions. 152-157 - Abhishek Roy, Peter J. Grossmann, Steven A. Vitale, Benton H. Calhoun:
A 1.3µW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications. 158-162 - Seogoo Lee, Dongwook Lee, Kyungtae Han, Emily Shriver, Lizy K. John, Andreas Gerstlauer:
Statistical quality modeling of approximate hardware. 163-168 - Meng-Yen Wu, Meng-Hsueh Chiang:
Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes. 169-172 - Lang Zhang, Hai Wang, Sheldon X.-D. Tan:
Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural network. 173-178 - Fatih Karabacak, Ümit Y. Ogras, Sule Ozev:
Detection of malicious hardware components in mobile platforms. 179-184 - Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan:
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. 185-191 - Haitong Tian, Martin D. F. Wong:
Performance evaluation considering mask misalignment in multiple patterning decomposition. 192-197 - Jiqin Zhou, Weigong Zhang, Keni Qiu, Xiaoyan Zhu:
UM-BUS: An online fault-tolerant bus for embedded systems. 198-204 - Ayushparth Sharma, Kusum Lata:
Low-leakage and process-variation-tolerant write-read disturb-free 9T SRA cell using CMOS and FinFETs. 205-210 - Tianhong Ye, Kuan W. A. Chee:
Ruggedness evaluation and design improvement of automotive power MOSFETs. 211-214 - Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi:
Device/system performance modeling of stacked lateral NWFET logic. 215-220 - Siddharth S. Bhargav, Andrew Kolb, Young H. Cho:
Accelerating physical level sub-component power simulation by online power partitioning. 221-226 - Hemanta Kumar Mondal, Sri Harsha Gade, Raghav Kishore, Shashwat Kaushik, Sujay Deb:
Power efficient router architecture for wireless Network-on-Chip. 227-233 - Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu:
Preventing integrated circuit piracy via custom encoding of hardware instruction set. 234-241 - Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Houman Homayoun:
Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates. 242-247 - Lalitha Sivaraj, Nurul Amziah Md Yunus, Mohd Nazim Mokhtar, Samsuzana Abd Aziz, Zurina Zainal Abidin, M. Iqbal Saripan, Fakhrul Zaman Rokhani:
Portable biosensor for chronic malaria detection. 248-251 - Javaneh Mohseni, Chenyun Pan, Azad Naeemi:
Performance modeling and optimization for on-chip interconnects in 3D memory arrays. 252-257 - Sriram Balasubramanian, Ninad Pimparkar, Mangesh Kushare, Vinayak Mahajan, Juhi Bansal, Takashi Shimizu, Vivek Joshi, Kun Qian, Arunima Dasgupta, Karthik Chandrasekaran, Chad Weintraub, Ali Icel:
Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications. 258-262 - Tiansong Cui, Ji Li, Alireza Shafaei, Shahin Nazarian, Massoud Pedram:
An efficient timing analysis model for 6T FinFET SRAM using current-based method. 263-268
Session 4B: Enabling 5nm Technology Node
- A. Asenov, Yangang Wang, Binjie Cheng, Xingsheng Wang, Plamen Asenov, Talib Al-Ameri, Vihar P. Georgiev:
Nanowire transistor solutions for 5nm and beyond. 269-274 - Praveen Raghavan, Marie Garcia Bardon, Peter Debacker, P. Schuddinck, Doyoung Jang, Rogier Baert, Diederik Verkest, Aaron Voon-Yew Thean:
5nm: Has the time for a device change come? 275-277 - Victor Moroz, Joanne Huang, Reza Arghavani:
Transistor design for 5nm and beyond: Slowing down electrons to speed up transistors. 278-283 - Fedor G. Pikus:
Decomposition technologies for advanced nodes. 284-288
Session 4C: Advanced Testing Concepts
- Panagiotis Sismanoglou, Dimitris Nikolos:
Low capture power dictionary-based test data compression. 289-294 - Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio:
Analysis of setup and hold margins inside silicon for advanced technology nodes. 295-300 - Hao Zheng, Yuting Cao, Sandip Ray, Jin Yang:
Protocol-guided analysis of post-silicon traces under limited observability. 301-306 - Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato:
Nonlinear delay-table approach for full-chip NBTI degradation prediction. 307-312
Session 5A: Embedded Systems
- Yuanwen Huang, Prabhat Mishra:
Reliability and energy-aware cache reconfiguration for embedded systems. 313-318 - Fazal Hameed, Mehdi Baradaran Tahoori:
Architecting STT Last-Level-Cache for performance and energy improvement. 319-324 - Anteneh Gebregiorgis, Fabian Oboril, Mehdi Baradaran Tahoori, Said Hamdioui:
Instruction cache aging mitigation through Instruction Set Encoding. 325-330 - Nga Dang, Zana Ghaderi, Moonju Park, Eli Bozorgzadeh:
Harvesting-aware adaptive energy management in solar-powered embedded systems. 331-337 - Ji Li, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram:
Negotiation-based resource provisioning and task scheduling algorithm for cloud systems. 338-343
Session 5B: Hardware and System Security
- Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
Digital IP protection using threshold voltage control. 344-349 - Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee:
Trojan detection in digital systems using current sensing of pulse propagation in logic gates. 350-355 - Steven Paley, Tamzidul Hoque, Swarup Bhunia:
Active protection against PCB physical tampering. 356-361 - Amey M. Kulkarni, Youngok K. Pino, Tinoosh Mohsenin:
SVM-based real-time hardware Trojan detection for many-core platform. 362-367 - Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
On testing physically unclonable functions for uniqueness. 368-373
Session 5C: Analog Design
- Miao Hu, John Paul Strachan, Zhiyong Li, R. Stanley Williams:
Dot-product engine as computing memory to accelerate machine learning algorithms. 374-379 - Khaja Ahmad Shaik, Kiyoo Itoh, Amara Amara:
0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus. 380-385 - Masahiro Kano, Toru Nakura, Kunihiro Asada:
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. 386-391 - Zheyu Liu, Fei Qiao, Qi Wei, Xinghua Yang, Yi Li, Huazhong Yang:
An ultra-fast and low-power design of analog circuit network for DoG pyramid construction of SIFT algorithm. 392-397
Session 6A: Design Optimization for Performance, Reliability, and Yield
- Divya Prasad, Chenyun Pan, Azad Naeemi:
Impact of interconnect variability on circuit performance in advanced technology nodes. 398-404 - Kareem Madkour, Sarah Mohamed, Dina Tantawy, Mohab Anis:
Hotspot detection using machine learning. 405-409 - Mohamed Baker Alawieh, Fa Wang, Rouwaida Kanj, Xin Li, Rajiv V. Joshi:
Efficient analog circuit optimization using sparse regression and error margining. 410-415 - Shilpa Pendyala, Srinivas Katkoori:
State encoding based NBTI optimization in finite state machines. 416-422
Session 6B: EDA for Design Exploration & Analysis Beyond Moore's Law
- Hua Xiang, Lakshmi N. Reddy, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu:
Gate movement for timing improvement on row based Dual-VDD designs. 423-429 - Jinyoung Lee, Sunghee Yun, Jeongha Kim, Dongsoo Kang, Jeongyeol Kim, Sanghoon Lee:
Multiple shift-vector importance sampling method using support vector machine and clustering for high-density DRAM designs. 430-436 - Toru Nakura, Kunihiro Asada:
Fully automated PLL compiler generating final GDS from specification. 437-442 - Zhong Guan, Malgorzata Marek-Sadowska:
AFD-based method for signal line EM reliability evaluation. 443-449
Session 6C: Sensors for lOT
- Shuang Zhu, Jingyi Song, Balaji Chellappa, Ali Enteshari, Tuo Shan, Mengxun He, Yun Chiu:
A smart ECG sensor with in-situ adaptive motion-artifact compensation for dry-contact wearable healthcare devices. 450-455 - Fatih Karabacak, Uwadiae Obahiagbon, Ümit Y. Ogras, Sule Ozev, Jennifer Blain Christen:
Making unreliable Chem-FET sensors smart via soft calibration. 456-461 - Hari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, Dinesh Kumar Sharma:
Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array. 462-467 - Tan Chee Phang, Mohammad Harris Mokhtar, Mohd Nazim Mokhtar, Fakhrul Zaman Rokhani:
Time-division multiple access based intra-body communication for wearable health tracker. 468-472
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