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2020 – today
- 2024
[i2]Zhiyu Chen, Ziyuan Wen, Weier Wan, Akhil Reddy Pakala, Yiwei Zou, Wei-Chen Wei, Zengyi Li, Yubei Chen, Kaiyuan Yang
:
PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro with In-Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout. CoRR abs/2407.12829 (2024)- 2022
- [j1]Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs:
A compute-in-memory chip based on resistive random-access memory. Nat. 608(7923): 504-512 (2022) - 2021
- [i1]Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs:
Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. CoRR abs/2108.07879 (2021) - 2020
- [c4]Rajkumar Kubendran, Weier Wan, Siddharth Joshi, H.-S. Philip Wong, Gert Cauwenberghs:
A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver. ICONS 2020: 18:1-18:4 - [c3]Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong:
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. ISSCC 2020: 498-500
2010 – 2019
- 2018
- [c2]William Hwang, Weier Wan, Subhasish Mitra, H.-S. Philip Wong:
Coming Up N3XT, After 2D Scaling of Si CMOS. ISCAS 2018: 1-5 - 2016
- [c1]Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong:
Neuromorphic architectures with electronic synapses. ISQED 2016: 118-123
Coauthor Index
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