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2010 – 2019
- 2019
[j5]Zhiyuan Yang
, Caleb Serafy, Tiantao Lu, Ankur Srivastava:
Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2022-2031 (2019)- 2017
- [j4]Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Sandeep Kumar Samal, Sung Kyu Lim, Ankur Srivastava:
TSV-Based 3-D ICs: Design Methods and Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1593-1619 (2017) - [j3]Tiantao Lu, Ankur Srivastava:
Low-Power Clock Tree Synthesis for 3D-ICs. ACM Trans. Design Autom. Electr. Syst. 22(3): 50:1-50:24 (2017) - [c7]Zhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava:
Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors. DAC 2017: 46:1-46:6 - 2016
- [j2]Yang Xie, Chongxi Bao, Caleb Serafy, Tiantao Lu, Ankur Srivastava, Mark M. Tehranipoor:
Security and Vulnerability Implications of 3D ICs. IEEE Trans. Multi Scale Comput. Syst. 2(2): 108-122 (2016) - [c6]Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Ankur Srivastava:
Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs. ISLPED 2016: 82-87 - [c5]Tiantao Lu, Zhiyuan Yang, Ankur Srivastava:
Electromigration-aware placement for 3D-ICs. ISQED 2016: 35-40 - [c4]Tiantao Lu, Zhiyuan Yang, Ankur Srivastava:
Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction. ISVLSI 2016: 158-163 - 2015
- [j1]Tiantao Lu, Ankur Srivastava:
Modeling and Layout Optimization for Tapered TSVs. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 3129-3132 (2015) - [c3]Tiantao Lu, Ankur Srivastava:
Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs. ACM Great Lakes Symposium on VLSI 2015: 27-32 - 2014
- [c2]Tiantao Lu, Ankur Srivastava:
Gated low-power clock tree synthesis for 3D-ICs. ISLPED 2014: 319-322 - 2013
- [c1]Tiantao Lu, Ankur Srivastava:
Detailed electrical and reliability study of tapered TSVs. 3DIC 2013: 1-7
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