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2010 – 2019
- 2017
[c7]Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix
:
Dynamic aging compensation and Safety measures in Automotive environment. IOLTS 2017: 106-112- [c6]Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, David Meyer, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix:
Cognitive approach to support dynamic aging compensation. ITC 2017: 1-7 - 2016
- [j1]Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick Girard:
An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. J. Electron. Test. 32(6): 721-733 (2016) - [c5]Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio:
Analysis of setup and hold margins inside silicon for advanced technology nodes. ISQED 2016: 295-300 - [c4]Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, Daniel Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, Maryline Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud:
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. VLSI Circuits 2016: 1-2 - 2015
- [c3]Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard:
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370
2000 – 2009
- 2005
- [c2]Steve Bourgeois, Hanna Martinsson, Quoc Cuong Pham, Sylvie Naudet:
A Practical Guide to Marker Based and Hybrid Visual Registration for AR Industrial Applications. CAIP 2005: 669-676 - 2002
- [c1]Thierry Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, David Roy, B. Borot, Nicolas Planes, Sylvie Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond:
Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC). MTDT 2002: 157-162
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