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ORCIDHamid Mahmoodi
Hamid Mahmoodi-Meimand
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- affiliation: San Francisco State University, USA
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2020 – today
- 2022
[j34]Gaurav Kolhe
, Tyler David Sheaves, Sai Manoj P. D., Hamid Mahmoodi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun:
Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation. ACM Trans. Design Autom. Electr. Syst. 27(6): 56:1-56:29 (2022)- [c66]Gaurav Kolhe, Tyler Sheaves, Kevin Immanuel Gubbi, Tejas Kadale, Setareh Rafatirad, Sai Manoj P. D., Avesta Sasan, Hamid Mahmoodi, Houman Homayoun:
Silicon validation of LUT-based logic-locked IP cores. DAC 2022: 1189-1194
2010 – 2019
- 2019
- [j33]Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, Hamid Mahmoodi:
RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2685-2698 (2019) - [c65]Fatemeh Tehranipoor, Nima Karimian, Mehran Mozaffari Kermani, Hamid Mahmoodi:
Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack. ACM Great Lakes Symposium on VLSI 2019: 335-338 - [c64]Gaurav Kolhe, Sai Manoj P. D., Setareh Rafatirad, Hamid Mahmoodi, Avesta Sasan, Houman Homayoun:
On Custom LUT-based Obfuscation. ACM Great Lakes Symposium on VLSI 2019: 477-482 - [c63]Gaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, Tyler David Sheaves, Hamid Mahmoodi, Sai Manoj P. D., Houman Homayoun, Setareh Rafatirad, Avesta Sasan:
Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality. ICCAD 2019: 1-8 - 2018
- [j32]Ted Winograd, Gaurav Shenoy, Hassan Salmani, Hamid Mahmoodi, Setareh Rafatirad, Houman Homayoun:
Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering. ACM Trans. Design Autom. Electr. Syst. 23(6): 76:1-76:21 (2018) - [c62]Aliyar Attaran, Tyler David Sheaves, Praveen Kumar Mugula, Hamid Mahmoodi:
Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC Designs. ACM Great Lakes Symposium on VLSI 2018: 507-510 - [i1]Fatemeh Tehranipoor, Nima Karimian, Mehran Mozaffari Kermani, Hamid Mahmoodi:
Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack. CoRR abs/1803.03332 (2018) - 2016
- [j31]Ragh Kuttappa, Houman Homayoun, Hassan Salmani, Hamid Mahmoodi:
Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging. Microelectron. Reliab. 62: 156-166 (2016) - [j30]Kolsoom Mehrabi, Behzad Ebrahimi, Roohollah Yarmand, Ali Afzali-Kusha, Hamid Mahmoodi:
Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs. Microelectron. Reliab. 65: 20-26 (2016) - [c61]Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Kris Gaj, Houman Homayoun:
Hybrid STT-CMOS designs for reverse-engineering prevention. DAC 2016: 88:1-88:6 - [c60]Aliyar Attaran, Hassan Salmani, Houman Homayoun, Hamid Mahmoodi:
Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations. ICCD 2016: 348-351 - [c59]Ragh Kuttappa, Houman Homayoun, Hassan Salmani, Hamid Mahmoodi:
Comparative analysis of robustness of spin transfer torque based look up tables under process variations. ISCAS 2016: 606-609 - [c58]Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Houman Homayoun:
Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates. ISQED 2016: 242-247 - [c57]Darya Almasi, Houman Homayoun, Hassan Salmani, Hamid Mahmoodi:
Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits. SoCC 2016: 259-264 - [c56]Seyed Saber Nabavi Larimi, Mehdi Kamal, Ali Afzali-Kusha, Hamid Mahmoodi:
Power and energy reduction of racetrack-based caches by exploiting shared shift operations. VLSI-SoC 2016: 1-6 - 2014
- [j29]Hamid Mahmoodi, Sridevi Srinivasan Lakshmipuram, Manish Arora, Yashar Asgarieh, Houman Homayoun, Bill Lin, Dean M. Tullsen:
Resistive Computation: A Critique. IEEE Comput. Archit. Lett. 13(2): 89-92 (2014) - [j28]Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Hooman Farkhani, Dag T. Wisland, Jens Kargaard Madsen, Hamid Mahmoodi, Kaushik Roy:
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology. Microelectron. J. 45(1): 23-34 (2014) - [j27]Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi:
Robust FinFET SRAM design based on dynamic back-gate voltage adjustment. Microelectron. Reliab. 54(11): 2604-2612 (2014) - [c55]Adarsh Reddy Ashammagari, Hamid Mahmoodi, Houman Homayoun:
Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design. DATE 2014: 1-6 - [c54]Adarsh Reddy Ashammagari, Hamid Mahmoodi, Tinoosh Mohsenin, Houman Homayoun:
Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors. ACM Great Lakes Symposium on VLSI 2014: 249-254 - 2013
- [j26]Farshad Moradi, Tuan Vu Cao, Elena I. Vatajelu, Ali Peiravi, Hamid Mahmoodi, Dag T. Wisland:
Domino logic designs for high-performance and leakage-tolerant applications. Integr. 46(3): 247-254 (2013) - [j25]Behrouz Afzal, Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi:
An analytical model for read static noise margin including soft oxide breakdown, negative and positive bias temperature instabilities. Microelectron. Reliab. 53(5): 670-675 (2013) - 2012
- [j24]Masaoud Houshmand Kaffashian, Reza Lotfi, Khalil Mafinezhad, Hamid Mahmoodi:
Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS. Microelectron. Reliab. 52(8): 1655-1659 (2012) - [j23]Behrouz Afzal, Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi:
Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability. Microelectron. Reliab. 52(12): 2948-2954 (2012) - [c53]Farshad Moradi, Dag T. Wisland, Jens Kargaard Madsen, Hamid Mahmoodi:
Flip-flop design using novel pulse generation technique. ICECS 2012: 685-688 - [c52]Roberto Menchaca, Hamid Mahmoodi:
Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS. ISQED 2012: 342-346 - [c51]Hamid Mahmoodi:
Reliability enhancement of power gating transistor under time dependent dielectric breakdown. VLSI-SoC 2012: 189-194 - [c50]Abhishek Guar, Hamid Mahmoodi:
Impact of technology scaling on performance of domino logic in nano-scale CMOS. VLSI-SoC 2012: 295-298 - 2011
- [j22]Masaoud Houshmand Kaffashian, Reza Lotfi, Khalil Mafinezhad, Hamid Mahmoodi:
An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS. IEICE Electron. Express 8(17): 1406-1411 (2011) - [j21]Masaoud Houshmand Kaffashian, Reza Lotfi, Khalil Mafinezhad, Hamid Mahmoodi:
Impact of NBTI on performance of domino logic circuits in nano-scale CMOS. Microelectron. J. 42(12): 1327-1334 (2011) - [c49]Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy:
Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. ICCD 2011: 326-331 - [c48]Vikram G. Rao, Hamid Mahmoodi:
Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology. ICCD 2011: 439-440 - [c47]Vish Ganti, Hamid Mahmoodi:
Comparative analysis of copper and CNT interconnects for H-tree clock distribution. ICCD 2011: 447-448 - [c46]Shreyas Kumar Krishnappa, Hamid Mahmoodi:
Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology. ISQED 2011: 384-389 - [p1]Hamid Mahmoodi:
Low-Power and Variation-Tolerant Memory Design. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 151-183 - 2010
- [j20]Minki Cho, Jason Schlessman, Hamid Mahmoodi, Marilyn Wolf, Saibal Mukhopadhyay:
Postsilicon Adaptation for Low-Power SRAM under Process Variation. IEEE Des. Test Comput. 27(6): 26-35 (2010) - [j19]Somnath Paul, Hamid Mahmoodi, Swarup Bhunia:
Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. ACM Trans. Design Autom. Electr. Syst. 15(2): 19:1-19:34 (2010) - [j18]Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy:
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. J. Signal Process. Syst. 58(2): 125-137 (2010) - [c45]Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy:
Data-dependant sense-amplifier flip-flop for low power applications. CICC 2010: 1-4 - [c44]Anuj Pushkarna, Hamid Mahmoodi:
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS. ACM Great Lakes Symposium on VLSI 2010: 373-376 - [c43]Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yngvar Berg, Tuan Vu Cao:
New SRAM design using body bias technique for ultra low power applications. ISQED 2010: 468-471 - [c42]Ankitchandra Shah, Hamid Mahmoodi:
Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits. SoCC 2010: 230-235 - [c41]Anuj Pushkarna, Sajna Raghavan, Hamid Mahmoodi:
Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies. SoCC 2010: 339-342
2000 – 2009
- 2009
- [j17]Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy:
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 33-44 (2009) - [c40]Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Snorre Aunet, Tuan Vu Cao, Ali Peiravi:
Ultra Low Power Full Adder Topologies. ISCAS 2009: 3158-3161 - [c39]Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao:
New subthreshold concepts in 65nm CMOS technology. ISQED 2009: 162-166 - [c38]Hamid Mahmoodi, Ali A. Jalali:
Virtual Age: Enabling Technologies and Trends. ITNG 2009: 999-1004 - [c37]Eli Lyons, Vish Ganti, Richard Goldman, Vazgen Melikyan, Hamid Mahmoodi:
Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library. MSE 2009: 45-48 - [c36]Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Tuan Vu Cao:
Improved write margin 6T-SRAM for low supply voltage applications. SoCC 2009: 223-226 - 2008
- [j16]Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy:
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electron. Test. 24(6): 577-590 (2008) - [j15]Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
A Low-Power SRAM Using Bit-Line Charge-Recycling. IEEE J. Solid State Circuits 43(2): 446-459 (2008) - [j14]Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 174-183 (2008) - [c35]Hamid Mahmoodi, Jeanne Trinko Mechler:
Session 8 - Characterization and test methods for device variability in nanoscale technologies. CICC 2008 - [c34]Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao:
65NM sub-threshold 11T-SRAM for ultra low voltage applications. SoCC 2008: 113-118 - 2007
- [j13]Saibal Mukhopadhyay, Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS. IEEE J. Solid State Circuits 42(6): 1370-1382 (2007) - [j12]Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy:
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1957-1966 (2007) - [c33]Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia:
Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD 2007: 401-404 - [c32]Vishwanadh Tirumalashetty, Hamid Mahmoodi:
Clock Gating and Negative Edge Triggering for Energy Recovery Clock. ISCAS 2007: 1141-1144 - [c31]Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
A low-power SRAM using bit-line charge-recycling technique. ISLPED 2007: 177-182 - [c30]Rajani Kuchipudi, Hamid Mahmoodi:
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. ISQED 2007: 27-32 - 2006
- [j11]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 183-192 (2006) - [j10]Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 1034-1039 (2006) - [c29]Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy:
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670 - [c28]Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia:
Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867 - [c27]Joyce Yeung, Hamid Mahmoodi:
Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies. SoCC 2006: 261-264 - [c26]Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici:
Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452 - 2005
- [j9]Hamid Mahmoodi, Saibal Mukhopadhyay, Kaushik Roy:
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits. IEEE J. Solid State Circuits 40(9): 1787-1796 (2005) - [j8]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1859-1880 (2005) - [j7]Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy:
A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 27-38 (2005) - [j6]Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy:
Low-power scan design using first-level supply gating. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 384-395 (2005) - [j5]Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy:
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1286-1295 (2005) - [c25]Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy:
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium 2005: 176-181 - [c24]Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484 - [c23]Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy:
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141 - [c22]Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy:
Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI 2005: 468-471 - [c21]Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi:
A high speed and leakage-tolerant domino logic for high fan-in gates. ACM Great Lakes Symposium on VLSI 2005: 478-481 - [c20]Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici:
Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224 - [c19]Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214 - [c18]Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS 2005: 171-176 - [c17]Aliakbar Ghadiri, Hamid Mahmoodi-Meimand:
Pre-capturing static pulsed flip-flops. ISCAS (3) 2005: 2421-2424 - [c16]Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy:
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458 - [c15]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED 2005: 490-495 - [c14]Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy:
A leakage control system for thermal stability during burn-in test. ITC 2005: 10 - [c13]Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy:
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. ITC 2005: 10 - [c12]Aliakbar Ghadiri, Hamid Mahmoodi-Meimand:
Dual-Edge Triggered Static Pulsed Flip-Flops. VLSI Design 2005: 846-849 - [c11]Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy:
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297 - 2004
- [j4]Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy:
Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid State Circuits 39(2): 348-357 (2004) - [j3]Hamid Mahmoodi-Meimand, Kaushik Roy:
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(3): 495-503 (2004) - [c10]Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Kaushik Roy:
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. CICC 2004: 17-20 - [c9]Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy:
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315 - [c8]Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy:
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. ICASSP (5) 2004: 97-100 - [c7]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Statistical design and optimization of SRAM cell for yield enhancement. ICCAD 2004: 10-13 - [c6]Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy:
A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65 - [c5]Hamid Mahmoodi-Meimand, Kaushik Roy:
Dual-edge triggered level converting flip-flops. ISCAS (2) 2004: 661-664 - [c4]Hamid Mahmoodi-Meimand, Kaushik Roy:
Data-retention flip-flops for power-down applications. ISCAS (2) 2004: 677-680 - 2003
- [j2]Kauschick Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand:
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(2): 305-327 (2003) - [c3]Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy:
Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED 2003: 54-59 - 2002
- [j1]Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand:
Leakage Current in Deep-Submicron CMOS Circuits. J. Circuits Syst. Comput. 11(6): 575-600 (2002) - [c2]Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy:
High performance and low power FIR filter design based on sharing multiplication. ISLPED 2002: 295-300 - 2001
- [c1]Hamid Mahmoodi-Meimand, Ali Afzali-Kusha:
Efficient power clock generation for adiabatic logic. ISCAS (4) 2001: 642-645
Coauthor Index
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