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ORCIDShreepad Panth
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2010 – 2019
- 2017
[j9]Shreepad Panth
, Sandeep Kumar Samal, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1265-1273 (2017)- [j8]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1716-1724 (2017) - 2016
- [j7]Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim:
Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1707-1720 (2016) - [j6]Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim:
More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2056-2067 (2016) - [c15]Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Monolithic 3D IC design: Power, performance, and area impact at 7nm. ISQED 2016: 41-48 - 2015
- [b1]Shreepad Panth:
Physical design methodologies for monolithic 3D ICs. Georgia Institute of Technology, Atlanta, GA, USA, 2015 - [j5]Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64(1): 112-125 (2015) - [j4]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 540-553 (2015) - [j3]Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim:
Scan Test of Die Logic in 3-D ICs Using TSV Probing. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 317-330 (2015) - [c14]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications. DAC 2015: 92:1-92:6 - [c13]Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim:
Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection. ICCAD 2015: 752-757 - 2014
- [j2]Shreepad Panth, Sandeep Kumar Samal, Yun Seop Yu, Sung Kyu Lim:
Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs. J. Inform. and Commun. Convergence Engineering 12(3): 186-192 (2014) - [c12]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations. DAC 2014: 62:1-62:6 - [c11]Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim:
Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs. DAC 2014: 206:1-206:6 - [c10]Shreepad A. Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Design and CAD methodologies for low power gate-level monolithic 3D ICs. ISLPED 2014: 171-176 - [c9]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs. ISPD 2014: 47-54 - 2013
- [j1]Junghee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Shreepad Panth, Sung Kyu Lim, Jongman Kim:
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1080-1093 (2013) - [c8]Shreepad Panth, Kambiz Samadi, Sung Kyu Lim:
Test-TSV estimation during 3D-IC partitioning. 3DIC 2013: 1-7 - [c7]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
High-density integration of functional modules using monolithic 3D-IC technology. ASP-DAC 2013: 681-686 - 2012
- [c6]Sergej Deutsch, Krishnendu Chakrabarty, Shreepad Panth, Sung Kyu Lim:
TSV Stress-Aware ATPG for 3D Stacked ICs. Asian Test Symposium 2012: 31-36 - [c5]Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190 - [c4]Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim:
Scan test of die logic in 3D ICs using TSV probing. ITC 2012: 1-8 - [c3]Shreepad Panth, Sung Kyu Lim:
Transition delay fault testing of 3D ICs with IR-drop study. VTS 2012: 270-275 - 2011
- [c2]Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, Hsien-Hsin S. Lee:
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. ICCD 2011: 90-95 - [c1]Shreepad Panth, Sung Kyu Lim:
Scan chain and power delivery network synthesis for pre-bond test of 3D ICs. VTS 2011: 26-31
Coauthor Index
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