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2010 – 2019
- 2015
[j8]Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty
, Sung Kyu Lim:
Scan Test of Die Logic in 3-D ICs Using TSV Probing. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 317-330 (2015)- 2014
- [b2]Brandon Noia, Krishnendu Chakrabarty:
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. Springer 2014, ISBN 978-3-319-02377-9, pp. I-XVIII, 1-245 - [b1]Brandon Noia:
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. Duke University, Durham, NC, USA, 2014 - [j7]Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye:
Test and Design-for-Testability Solutions for 3D Integrated Circuits. Inf. Media Technol. 9(4): 386-403 (2014) - [j6]Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye:
Test and Design-for-Testability Solutions for 3D Integrated Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 7: 56-73 (2014) - [j5]Brandon Noia, Krishnendu Chakrabarty:
Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 464-475 (2014) - 2013
- [j4]Brandon Noia, Krishnendu Chakrabarty:
Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 547-558 (2013) - [c10]Zhenqian Zhang, Brandon Noia, Krishnendu Chakrabarty, Paul D. Franzon:
Face-to-face bus design with built-in self-test in 3D ICs. 3DIC 2013: 1-7 - [c9]Brandon Noia, Krishnendu Chakrabarty:
Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs. VTS 2013: 1-6 - 2012
- [j3]Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen:
Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J. Electron. Test. 28(1): 103-120 (2012) - [c8]Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim:
Scan test of die logic in 3D ICs using TSV probing. ITC 2012: 1-8 - 2011
- [j2]Brandon Noia, Krishnendu Chakrabarty:
Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips. IET Comput. Digit. Tech. 5(3): 186-197 (2011) - [j1]Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree:
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1705-1718 (2011) - [c7]Brandon Noia, Krishnendu Chakrabarty:
Pre-bond testing of die logic and TSVs in high performance 3D-SICs. 3DIC 2011: 1-5 - [c6]Brandon Noia, Krishnendu Chakrabarty:
Identification of Defective TSVs in Pre-Bond Testing of 3D ICs. Asian Test Symposium 2011: 187-194 - [c5]Brandon Noia, Krishnendu Chakrabarty:
Testing and Design-for-Testability Techniques for 3D Integrated Circuits. Asian Test Symposium 2011: 474-479 - [c4]Brandon Noia, Krishnendu Chakrabarty:
Pre-bond probing of TSVs in 3D stacked ICs. ITC 2011: 1-10 - 2010
- [c3]Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree:
Test-architecture optimization for TSV-based 3D stacked ICs. ETS 2010: 24-29 - [c2]Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen:
Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. ITC 2010: 193-201
2000 – 2009
- 2009
- [c1]Brandon Noia, Krishnendu Chakrabarty, Yuan Xie:
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. ICCD 2009: 70-77
Coauthor Index
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