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ORCIDIntegration, Volume 7
Volume 7, Number 1, April 1989
- Lambert Spaanenburg:
Editorial. vii - Jer-Min Jou, Jau-Yien Lee:
A new 3-layer rectilinear area router with obstacle avoidance. 1-20 - Sun Young Hwang:
Incremental algorithms for digital simulation. 21-34 - Hartmut Grabinski:
An algorithm for computing the signal propagation on lossy VLSI interconnect systems in the time domain. 35-48 - Sharad C. Seth, Vishwani D. Agrawal:
A new model for computation of probabilistic testability in combinational circuits. 49-75 - P. K. Lim, Maher A. Sid-Ahmed, Graham A. Jullien:
VLSI implementation of a digital image threshold selection architecture. 77-91
Volume 7, Number 2, August 1989
- Lambert Spaanenburg:
Editorial. 101 - Lionel M. Ni, Youran Lan, Abdol-Hossein Esfahanian:
A VLSI router design for hypercube multiprocessors. 103-125 - Francesco Curatelli, P. Antognetti:
A reconfigurable wiring algorithm for three-layer maze routing. 127-149 - Richard J. Enbody, David H. C. Du:
SPYDER: a serial/parallel goal-directed router. 151-187 - Thomas R. Mueller, D. F. Wong
, C. L. Liu:
An enhanced bottom-up algorithm for floorplan design. 189-201
Volume 7, Number 3, September 1989
- Lambert Spaanenburg:
Editorial. 211 - Reiner Kolla, Paul Molitor:
A note on hierarchical layer-assignment. 213-230 - Yue-Sun Kuo, T. C. Chern, Wei-Kuan Shih:
Fast algorithm for optimal layer assignment. 231-245 - Jeffrey J. Joyce:
Formal specification and verification of microprocessor systems. 247-266 - Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri:
Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach. 267-281 - C. P. Ravikumar, Sarma Sastry:
A hardware accelerator for hierarchical VLSI routing. 283-302 - Alaaeldin A. M. Amin, Kent F. Smith:
Test generation and fault detection for VLSI PPL circuits. 303-324 - Sharad C. Seth, Vishwani D. Agrawal:
A new model for computation of probabilistic testability in combinational circuits. 325
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