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ORCIDIntegration, Volume 15
Volume 15, Number 1, July 1993
- Pranav Ashar, Srinivas Devadas, Kurt Keutzer:
Path-delay-fault testability properties of multiplexor-based networks. 1-23 - Mark Anderson, Francine Berman:
Assessing partitioning/ scheduling/storage trade-offs for regular iterative algorithms. 25-50 - S. J. Su, Yue-Sun Kuo, J. C. Tsay:
Adaptable quad tree techniques. 51-71 - Paul Molitor
:
A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization. 73-95 - Dominique Lavenier:
An integrated 2D systolic array for spelling correction. 97-111
Volume 15, Number 2, October 1993
- Wayne H. Wolf:
FSM decomposition for pipelined data. 117-131 - Amiya Nayak, Linda Pagli, Nicola Santoro:
Efficient construction of catastrophic patterns for VLSI reconfigurable arrays. 133-150 - Spyros Tragoudas, Ioannis G. Tollis:
River routing and density minimization for channels with interchangeable terminals. 151-178 - Ting-Chi Wang, D. F. Wong:
Graph-based techniques to speed up floorplan area optimization. 179-199 - Giacomo Buonanno, Fabrizio Lombardi, Donatella Sciuto, Yinan N. Shen:
Fault detection in TFCMOS/DFCMOS combinational gates. 201-227
Volume 15, Number 3, October 1993
- Ganesh Gopalakrishnan, Erik Brunvand:
Guest editors' introduction to the special issue on asynchronous systems. 233-239 - Steven M. Nowick, Mark E. Dean, David L. Dill, Mark Horowitz:
The design of a high-performance cache controller: a case study in asynchronous synthesis. 241-262 - Tam-Anh Chu:
CLASS: a CAD system for automatic synthesis and verification of asynchronous finite state machines. 263-289 - Christian D. Nielsen, Alain J. Martin:
Design of a delay-insensitive multiply-accumulate unit. 291-311 - Jens Sparsø, Jørgen Staunstrup:
Delay-insensitive multi-ring structures. 313-340 - Bill Coates, Al Davis, Ken Stevens:
The Post Office experience: designing a large asynchronous chip. 341-366
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