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2020 – today
- 2023
[c17]Chen-Yu Lee, Chun-Liang Li, Hao Zhang, Timothy Dozat, Vincent Perot, Guolong Su, Xiang Zhang, Kihyuk Sohn, Nikolay Glushnev, Renshen Wang, Joshua Ainslie, Shangbang Long, Siyang Qin, Yasuhisa Fujii, Nan Hua, Tomas Pfister:
FormNetV2: Multimodal Graph Contrastive Learning for Form Document Information Extraction. ACL (1) 2023: 9011-9026- [c16]Renshen Wang, Yasuhisa Fujii, Alessandro Bissacco:
Text Reading Order in Uncontrolled Conditions by Sparse Graph Segmentation. ICDAR (6) 2023: 3-21 - [i6]Chen-Yu Lee, Chun-Liang Li, Hao Zhang, Timothy Dozat, Vincent Perot, Guolong Su, Xiang Zhang, Kihyuk Sohn, Nikolai Glushnev, Renshen Wang, Joshua Ainslie, Shangbang Long, Siyang Qin, Yasuhisa Fujii, Nan Hua, Tomas Pfister:
FormNetV2: Multimodal Graph Contrastive Learning for Form Document Information Extraction. CoRR abs/2305.02549 (2023) - [i5]Renshen Wang, Yasuhisa Fujii, Alessandro Bissacco:
Text Reading Order in Uncontrolled Conditions by Sparse Graph Segmentation. CoRR abs/2305.02577 (2023) - 2022
- [c15]Chen-Yu Lee, Chun-Liang Li, Timothy Dozat, Vincent Perot, Guolong Su, Nan Hua, Joshua Ainslie, Renshen Wang, Yasuhisa Fujii, Tomas Pfister:
FormNet: Structural Encoding beyond Sequential Modeling in Form Document Information Extraction. ACL (1) 2022: 3735-3754 - [c14]Shuang Liu, Renshen Wang, Michalis Raptis, Yasuhisa Fujii:
Unified Line and Paragraph Detection by Graph Convolutional Networks. DAS 2022: 33-47 - [c13]Renshen Wang, Yasuhisa Fujii, Ashok C. Popat:
Post-OCR Paragraph Recognition by Graph Convolutional Networks. WACV 2022: 2533-2542 - [i4]Chen-Yu Lee, Chun-Liang Li, Timothy Dozat, Vincent Perot, Guolong Su, Nan Hua, Joshua Ainslie, Renshen Wang, Yasuhisa Fujii, Tomas Pfister:
FormNet: Structural Encoding beyond Sequential Modeling in Form Document Information Extraction. CoRR abs/2203.08411 (2022) - [i3]Shuang Liu, Renshen Wang, Michalis Raptis, Yasuhisa Fujii:
Unified Line and Paragraph Detection by Graph Convolutional Networks. CoRR abs/2203.09638 (2022) - 2021
- [c12]Chen-Yu Lee, Chun-Liang Li, Chu Wang, Renshen Wang, Yasuhisa Fujii, Siyang Qin, Ashok C. Popat, Tomas Pfister:
ROPE: Reading Order Equivariant Positional Encoding for Graph-based Document Information Extraction. ACL/IJCNLP (2) 2021: 314-321 - [i2]Renshen Wang, Yasuhisa Fujii, Ashok C. Popat:
General-Purpose OCR Paragraph Identification by Graph Convolution Networks. CoRR abs/2101.12741 (2021) - [i1]Chen-Yu Lee, Chun-Liang Li, Chu Wang, Renshen Wang, Yasuhisa Fujii, Siyang Qin, Ashok C. Popat, Tomas Pfister:
ROPE: Reading Order Equivariant Positional Encoding for Graph-based Document Information Extraction. CoRR abs/2106.10786 (2021)
2010 – 2019
- 2012
- [c11]Renshen Wang, Nimish Shah:
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip. ISPD 2012: 187-192 - 2011
- [j2]Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 167-179 (2011) - 2010
- [b1]Renshen Wang:
Physical planning to embrace interconnect dominance in power and performance. University of California, San Diego, USA, 2010 - [j1]Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng:
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. ACM Trans. Design Autom. Electr. Syst. 15(4): 33:1-33:22 (2010) - [c10]Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng:
Physical synthesis of bus matrix for high bandwidth low power on-chip communications. ISPD 2010: 91-96
2000 – 2009
- 2009
- [c9]Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng:
Noise minimization during power-up stage for a multi-domain power network. ASP-DAC 2009: 391-396 - [c8]Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng:
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. DAC 2009: 166-171 - [c7]Renshen Wang, Chung-Kuan Cheng:
Octilinear redistributive routing in bump arrays. ACM Great Lakes Symposium on VLSI 2009: 191-196 - [c6]Renshen Wang, Chung-Kuan Cheng:
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. ACM Great Lakes Symposium on VLSI 2009: 257-262 - [c5]Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng:
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations. ICCD 2009: 23-28 - 2008
- [c4]Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng:
Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects 2008: 51-56 - [c3]Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng:
3-D floorplanning using labeled tree and dual sequences. ISPD 2008: 54-59 - 2006
- [c2]Renshen Wang, Rui Shi, Chung-Kuan Cheng:
Layer minimization of escape routing in area array packaging. ICCAD 2006: 815-819 - 2005
- [c1]Renshen Wang, Sheqin Dong, Xianlong Hong:
An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC 2005: 1115-1118
Coauthor Index
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