"Cell-based layout techniques supporting gate-level voltage scaling for low ..."

Chingwei Yeh, Yin-Shuin Kang (2001)

> Home

Details and statistics

DOI: 10.1109/92.974912

access: closed

type: Journal Article

metadata version: 2020-03-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/YehK01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/YehK01
Chingwei Yeh, Yin-Shuin Kang:
Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 983-986 (2001)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.