"Cross-matching caches: Dynamic timing calibration and bit-level ..."

Po-Hao Wang et al. (2016)

> Home

Details and statistics

DOI: 10.1016/J.VLSI.2016.01.001

access: closed

type: Journal Article

metadata version: 2020-02-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/integration/WangTTLWC16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/integration/WangTTLWC16
Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. 54: 24-36 (2016)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.