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ORCIDGianluca Piccinini
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2020 – today
- 2023
[j24]Davide Costa, Mario Simoni
, Gianluca Piccinini, Mariagrazia Graziano:
Advances in Modeling of Noisy Quantum Computers: Spin Qubits in Semiconductor Quantum Dots. IEEE Access 11: 98875-98913 (2023)- [j23]Yuri Ardesi, Umberto Garlando, Fabrizio Riente, Giuliana Beretta, Gianluca Piccinini, Mariagrazia Graziano:
Taming Molecular Field-Coupling for Nanocomputing Design. ACM J. Emerg. Technol. Comput. Syst. 19(1): 1:1-1:24 (2023) - [j22]Fabrizio Mo, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, Mariagrazia Graziano:
Design of Pyrrole-Based Gate-Controlled Molecular Junctions Optimized for Single-Molecule Aflatoxin B1 Detection. Sensors 23(3): 1687 (2023) - 2021
- [j21]Yuri Ardesi, Giovanna Turvani, Mariagrazia Graziano, Gianluca Piccinini:
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 558-567 (2021) - [c28]Yuri Ardesi, Giuliana Beretta, Christian Fabiano, Mariagrazia Graziano, Gianluca Piccinini:
A Reconfigurable Field-Coupled Nanocomputing Paradigm on Uniform Molecular Monolayers. ICRC 2021: 124-128 - 2020
- [j20]Yuri Ardesi, Ruiyu Wang, Giovanna Turvani, Gianluca Piccinini, Mariagrazia Graziano:
SCERPA: A Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled Nanocomputing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2749-2760 (2020)
2010 – 2019
- 2019
- [c27]Yuri Ardesi, Luca Gnoli, Mariagrazia Graziano, Gianluca Piccinini:
Bistable Propagation of Monostable Molecules in Molecular Field-Coupled Nanocomputing. PRIME 2019: 225-228 - 2018
- [j19]Malik Ashter Mehdy, Aleandro Antidormi, Mariagrazia Graziano, Gianluca Piccinini:
Nanoarrays for Systolic Biosequence Analysis. J. Circuits Syst. Comput. 27(12): 1850194:1-1850194:26 (2018) - 2015
- [j18]Mariagrazia Graziano, Azzurra Pulimeno, Ruiyu Wang, Xiang Wei, Massimo Ruo Roch, Gianluca Piccinini:
Process Variability and Electrostatic Analysis of Molecular QCA. ACM J. Emerg. Technol. Comput. Syst. 12(2): 18:1-18:23 (2015) - [j17]Maurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini:
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2103-2113 (2015) - 2014
- [j16]Carlo Condo, Maurizio Martina, Gianluca Piccinini, Guido Masera:
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced. IEEE Signal Process. Lett. 21(11): 1380-1384 (2014) - [j15]Guoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini:
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 890-894 (2014) - [c26]Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini:
Molecular transistor circuits: From device model to circuit simulation. NANOARCH 2014: 129-134 - [p1]Azzurra Pulimeno, Mariagrazia Graziano, Aleandro Antidormi, Ruiyu Wang, Ali Zahir, Gianluca Piccinini:
Understanding a Bisferrocene Molecular QCA Wire. Field-Coupled Nanocomputing 2014: 307-338 - 2013
- [c25]Ismael Rattalino, Paolo Motto Ros, Irene Taurino, Fernando Cortes-Salazar, Gianluca Piccinini, Danilo Demarchi, Giovanni De Micheli, Sandro Carrara:
Nanogap-based enzymatic-free electrochemical detection of glucose. BioCAS 2013: 130-133 - [c24]Azzurra Pulimeno, Mariagrazia Graziano, Ruiyu Wang, Danilo Demarchi, Gianluca Piccinini:
Charge distribution in a molecular QCA wire based on bis-ferrocene molecules. NANOARCH 2013: 42-43 - 2012
- [j14]Azzurra Pulimeno, Mariagrazia Graziano, Gianluca Piccinini:
UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1341-1346 (2012) - 2010
- [j13]Maurizio Martina, Guido Masera, Gianluca Piccinini:
Scalable low-complexity B-spline discrete wavelet transform architecture. IET Circuits Devices Syst. 4(2): 159-167 (2010)
2000 – 2009
- 2008
- [j12]Mariagrazia Graziano, Gianluca Piccinini:
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks. Integr. 41(4): 524-538 (2008) - 2004
- [j11]Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectron. J. 35(10): 849-857 (2004) - [j10]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 349-358 (2004) - 2003
- [j9]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Coupled electro-thermal modeling and optimization of clock networks. Microelectron. J. 34(12): 1175-1185 (2003) - [j8]Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. J. VLSI Signal Process. 35(2): 137-153 (2003) - [c23]Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni:
Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA 2003: 246 - [c22]Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS 2003: 90-100 - [c21]M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS 2003: 121-130 - 2002
- [j7]Guido Masera, Marco Mazza, Gianluca Piccinini, Fabrizio Viglione, Maurizio Zamboni:
Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 279-285 (2002) - [c20]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL 2002: 332-339 - [c19]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
Reconfigurable DSP IP for multimedia applications. ICASSP 2002: 4179 - [c18]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
System architecture for error-resilient, embedded JPEG2000 wireless delivery. DSP 2002: 211-218 - [c17]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
Embedded IWT evaluation in reconfigurable wireless sensor network. ICECS 2002: 855-858 - [c16]Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni:
Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS 2002: 198-208 - 2001
- [c15]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
JPEG 2000: finite precision representation and hardware implications. ICECS 2001: 875-878 - [c14]Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni:
Reconfigurable coprocessor based JPEG 2000 implementation. ICECS 2001: 1227-1230 - [c13]Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED 2001: 287-290 - [c12]Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Hierarchical power supply noise evaluation for early power grid design prediction. SLIP 2001: 183-188 - [c11]Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design 2001: 524-530 - 2000
- [c10]Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A 50 Mbit/s Iterative Turbo-Decoder. DATE 2000: 176-180 - [c9]Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A high accuracy-low complexity model for CMOS delays. ISCAS 2000: 455-458 - [c8]Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
Noise Safety Design Methodologies. ISQED 2000: 157-
1990 – 1999
- 1999
- [j6]Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
VLSI architectures for turbo codes. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 369-379 (1999) - [c7]Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics 1999: 51-54 - [c6]Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI 1999: 82-85 - [c5]Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A global optimization tool for CMOS logic circuits. ICECS 1999: 1671-1674 - 1998
- [c4]A. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni:
A 500 MHz 2d-DWT VLSI processor. EUSIPCO 1998: 1-4 - [c3]Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni:
Fanout optimization under a submicron transistor-level delay model. ICCAD 1998: 551-556 - 1997
- [j5]Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni:
A comprehensive submicrometer MOST delay model and its application to CMOS buffers. IEEE J. Solid State Circuits 32(8): 1254-1262 (1997) - 1996
- [c2]F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. EUSIPCO 1996: 1-4 - 1993
- [j4]Livio Baldi, Pierluigi Civera, Angela Iurlaro, Guido Masera, Andrea Pagni, Gianluca Piccinini, Rinaldo Poluzzi, Massimo Ruo Roch, Maurizio Zamboni:
PROXIMA: PROlog eXecutIon MAchine. IEEE J. Solid State Circuits 28(3): 362-370 (1993) - 1992
- [j3]Guido Albertengo, Pierluigi Civera, Renato Lo Cigno, Gianluca Piccinini, Maurizio Zamboni, Flaminio Borgonovo, Luigi Fratta, Giuseppe Panizzardi:
Deflection network: Principles, implementation, services. Eur. Trans. Telecommun. 3(2): 195-206 (1992)
1980 – 1989
- 1989
- [j2]Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni:
Implementation studies for a VLSI Prolog coprocessor. IEEE Micro 9(1): 10-23 (1989) - 1987
- [j1]Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni:
Design considerations on a VLSI Prolog interpreter. Microprocess. Microprogramming 21(1-5): 267-273 (1987) - [c1]Pierluigi Civera, Franco Maddaleno, Gianluca Piccinini, Maurizio Zamboni:
An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. ISCA 1987: 117-126
Coauthor Index
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