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2020 – today
- 2023
[c6]Yanzhao Wang
, Fei Xie, Zhenkun Yang, Pasquale Cocchini, Jin Yang:
An Equivalence Checking Framework for Agile Hardware Design. ASP-DAC 2023: 26-32- [c5]Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang:
An Automated Verification Framework for HalideIR-Based Compiler Transformations. DATE 2023: 1-6 - [i3]Zhenkun Yang, Wen Wang, Jeremy Casas, Pasquale Cocchini, Jin Yang:
Towards A Correct-by-Construction FHE Model. IACR Cryptol. ePrint Arch. 2023: 281 (2023) - 2022
- [c4]Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang:
Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC 2022: 1351-1354 - 2021
- [i2]Yash Akhauri, Adithya Niranjan, J. Pablo Muñoz, Suvadeep Banerjee, Abhijit Davare, Pasquale Cocchini, Anton A. Sorokin, Ravi Iyer, Nilesh Jain:
RHNAS: Realizable Hardware and Neural Architecture Search. CoRR abs/2106.09180 (2021) - [i1]Suvadeep Banerjee, Steve Burns, Pasquale Cocchini, Abhijit Davare, Shweta Jain, Desmond Kirkpatrick, Anton Sorokin, Jin Yang, Zhenkun Yang:
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration. CoRR abs/2111.15024 (2021)
2000 – 2009
- 2004
- [j4]Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick:
Repeater scaling and its impact on CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 451-463 (2004) - 2003
- [j3]Pasquale Cocchini:
A methodology for optimal repeater insertion in pipelined interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12): 1613-1624 (2003) - [c3]Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick:
The scaling challenge: can correct-by-construction design help? ISPD 2003: 51-58 - 2002
- [c2]Pasquale Cocchini:
Concurrent flip-flop and repeater insertion for high performance integrated circuits. ICCAD 2002: 268-273 - 2000
- [j2]Pasquale Cocchini, Massoud Pedram:
Fanout optimization using bipolar LT-trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 339-349 (2000)
1990 – 1999
- 1998
- [c1]Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni:
Fanout optimization under a submicron transistor-level delay model. ICCAD 1998: 551-556 - 1997
- [j1]Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni:
A comprehensive submicrometer MOST delay model and its application to CMOS buffers. IEEE J. Solid State Circuits 32(8): 1254-1262 (1997)
Coauthor Index
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