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2020 – today
- 2024
[c11]Ruixin Wang
, Minghai Lu, Cody Hao Yu, Yi-Hsiang Lai, Tianyi Zhang:
Automated Deep Learning Optimization via DSL-Based Source Code Transformation. ISSTA 2024: 479-490- [i2]Ruixin Wang, Minghai Lu, Cody Hao Yu, Yi-Hsiang Lai, Tianyi Zhang:
Automated Deep Learning Optimization via DSL-Based Source Code Transformation. CoRR abs/2405.03067 (2024) - 2022
- [c10]Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang:
Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC 2022: 1351-1354 - [c9]Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang:
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. FPGA 2022: 78-88 - 2021
- [j2]Yi-Hsiang Lai, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, Zhiru Zhang:
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. ACM Trans. Reconfigurable Technol. Syst. 14(4): 17:1-17:39 (2021) - [i1]Zhi Chen, Cody Hao Yu, Trevor Morris, Jorn Tuyls, Yi-Hsiang Lai, Jared Roesch, Elliott Delaye, Vin Sharma, Yida Wang:
Bring Your Own Codegen to Deep Learning Compiler. CoRR abs/2105.03215 (2021) - 2020
- [c8]Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey:
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD 2020: 73:1-73:9
2010 – 2019
- 2019
- [c7]Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang:
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA 2019: 242-251 - 2018
- [c6]Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang:
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. FPGA 2018: 269-278 - 2016
- [j1]Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang:
Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1797-1810 (2016) - [c5]Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang:
Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. ICCAD 2016: 5 - 2015
- [c4]Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang:
Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. ICCAD 2015: 434-441 - [c3]Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang:
SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. ICCAD 2015: 442-449 - [c2]Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang:
A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. ICCAD 2015: 736-743 - 2014
- [c1]Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang:
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. DAC 2014: 192:1-192:6
Coauthor Index
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