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2020 – today
- 2025
[c11]Jinming Zhuang
, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou:
ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. FPGA 2025: 92-102- 2024
- [j2]Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng, Mengjia Dai, Zhiru Zhang:
Allo: A Programming Model for Composable Accelerator Design. Proc. ACM Program. Lang. 8(PLDI): 593-620 (2024) - [c10]Hongzheng Chen, Cody Hao Yu, Shuai Zheng, Zhen Zhang, Zhiru Zhang, Yida Wang:
Slapo: A Schedule Language for Progressive Optimization of Large Deep Learning Model Training. ASPLOS (2) 2024: 1095-1111 - [c9]Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez, Zhiru Zhang:
Formal Verification of Source-to-Source Transformations for HLS. FPGA 2024: 97-107 - [c8]Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang:
A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. FPGA 2024: 185 - [i6]Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng, Mengjia Dai, Zhiru Zhang:
Allo: A Programming Model for Composable Accelerator Design. CoRR abs/2404.04815 (2024) - 2023
- [c7]Tianfeng Liu, Yangrui Chen, Dan Li, Chuan Wu, Yibo Zhu, Jun He, Yanghua Peng, Hongzheng Chen, Hongzhi Chen, Chuanxiong Guo:
BGL: GPU-Efficient GNN Training by Optimizing Graph Data I/O and Preprocessing. NSDI 2023: 103-118 - [i5]Hongzheng Chen, Cody Hao Yu, Shuai Zheng, Zhen Zhang, Zhiru Zhang, Yida Wang:
Decoupled Model Schedule for Deep Learning Training. CoRR abs/2302.08005 (2023) - [i4]Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang:
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference. CoRR abs/2312.15159 (2023) - 2022
- [c6]Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang:
Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC 2022: 1351-1354 - [c5]Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang:
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. FPGA 2022: 78-88 - [i3]Yaohui Cai, Weizhe Hua, Hongzheng Chen, G. Edward Suh, Christopher De Sa, Zhiru Zhang:
Structured Pruning is All You Need for Pruning CNNs at Initialization. CoRR abs/2203.02549 (2022) - 2021
- [c4]Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang:
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. FPGA 2021: 171-182 - [c3]Hongzheng Chen, Minghua Shen, Nong Xiao, Yutong Lu:
Krill: a compiler and runtime system for concurrent graph processing. SC 2021: 51 - [i2]Tianfeng Liu, Yangrui Chen, Dan Li, Chuan Wu, Yibo Zhu, Jun He, Yanghua Peng, Hongzheng Chen, Hongzhi Chen, Chuanxiong Guo:
BGL: GPU-Efficient GNN Training by Optimizing Graph Data I/O and Preprocessing. CoRR abs/2112.08541 (2021) - 2020
- [j1]Minghua Shen, Hongzheng Chen, Nong Xiao:
Entropy-Directed Scheduling for FPGA High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2588-2601 (2020) - [i1]Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang:
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. CoRR abs/2012.12206 (2020)
2010 – 2019
- 2019
- [c2]Hongzheng Chen, Minghua Shen:
A Deep-Reinforcement-Learning-Based Scheduler for High-Level Synthesis. FPGA 2019: 117 - [c1]Hongzheng Chen, Minghua Shen:
A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS. ICCAD 2019: 1-8
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