default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID12th ASYNC 2006: Grenoble, France
- 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France. IEEE Computer Society 2006, ISBN 0-7695-2498-2
Invited Talk 1
- Nobuo Karaki:
Asynchronous Design: An Enabler for Flexible Microelectronics.
Session 1: Interfacing and Synchronization
- David Kinniment, Keith Heron, Gordon Russell:
Measuring Deep Metastability. 2-11 - Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel:
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter. 12-22 - Jo C. Ebergen, Alex Chow, Bill Coates, Justin Schauer, David Hopkins:
An Asynchronous High-Throughput Control Circuit For Proximity Communication. 23-33
Session 2: Fault-Tolerance and Testing
- Song Peng, Rajit Manohar:
Self-Healing Asynchronous Arrays. 34-45 - Gennette Gill, Ankur Agiwal, Montek Singh, Feng Shi, Yiorgos Makris
:
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines. 46-56 - Feng Shi, Yiorgos Makris:
A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. 57-67
Session 3: Novel Architectures and Design Practices
- Masashi Imai, Takashi Nanya:
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. 68-77 - Luca Necchi, Luciano Lavagno, Davide Pandini, Laura Vanzago:
An ultra-low energy asynchronous processor for Wireless Sensor Networks. 78-85 - D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin:
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. 86-97
Invited Talk 2
- Jean-Pierre Schoellkopf:
ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System Architecture.
Session 4: Interconnect and Communcations
- Mark R. Greenstreet, Jihong Ren:
Surfing Interconnect. 98-106 - Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Oleg V. Maevsky:
Multiple-Rail Phase-Encoding for NoC. 107-116 - Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny:
Fast Asynchronous Shift Register for Bit-Serial Communication. 117-127
Session 5: Synthesis
- Cheoljoo Jeong, Steven M. Nowick:
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks. 128-137 - William B. Toms, David A. Edwards, Andrew Bardsley:
Synthesising Heterogeneously Encoded Systems. 138-149
Invited Talk 3
- Ferdinand Peper:
Asynchronous Architectures for Nanometer Scales.
Session 6: Design and Architectures for GALS
- Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
GALS at ETH Zurich: Success or Failure. 150-159 - Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan:
Interface Design for Rationally Clocked GALS Systems. 160-171 - Edith Beigné, Pascal Vivet:
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. 172-183
Session 7: Slack Matching
- Peter A. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies:
Slack Matching Asynchronous Designs. 184-194 - Piyush Prakash, Alain J. Martin:
Slack Matching Quasi Delay-Insensitive Circuits. 195-204
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-22 19:50 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
