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2020 – today
- 2021
[c45]Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara:
An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring. GCCE 2021: 909-910- 2020
- [j9]Toshiki Kanamoto
, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, Masashi Imai:
A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis. IEICE Electron. Express 17(14): 20200198 (2020) - [c44]Tomohiro Yoneda, Masashi Imai:
Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices. ASYNC 2020: 102-110
2010 – 2019
- 2019
- [c43]Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai:
Hardware Trojan Insertion and Detection in Asynchronous Circuits. ASYNC 2019: 134-143 - [c42]Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai:
A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck. MWSCAS 2019: 1085-1088 - [i1]Tomohiro Yoneda, Peter A. Beerel, Alex Yakovlev, Masashi Imai:
Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133). NII Shonan Meet. Rep. 2019 (2019) - 2018
- [j8]Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82: 46-61 (2018) - [c41]Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda:
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. ASYNC 2018: 1-8 - 2017
- [j7]Hiroshi Saito, Masashi Imai, Tomohiro Yoneda:
Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1363-1373 (2017) - [c40]Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda:
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC 2017: 118-125 - [c39]Kaoru Furumi, Masashi Imai, Atsushi Kurokawa:
Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs. ISQED 2017: 283-288 - 2016
- [c38]Hiroshi Saito, Masashi Imai, Tomohiro Yoneda:
A task allocation method for the DTTR scheme based on task scheduling of fault patterns. ISCAS 2016: 237-240 - [c37]Hiroshi Saito, Masashi Imai, Tomohiro Yoneda:
A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. MCSoC 2016: 169-176 - [c36]Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda:
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS 2016: 1-8 - 2015
- [j6]Masashi Imai, Tomohiro Yoneda:
Novel Implementation Method of Multiple-Way Asynchronous Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1519-1528 (2015) - [j5]Nanako Niioka, Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa:
Signal Propagation Delay Model in Vertically Stacked Chips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2614-2624 (2015) - [c35]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise:
Dependable real-time task execution scheme for a many-core platform. DFTS 2015: 197-204 - [c34]Tomohiro Yoneda, Masashi Imai:
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. ICCD 2015: 395-398 - [c33]Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa:
Clock skew reduction for stacked chips using multiple source buffers. ISCIT 2015: 327-330 - [c32]Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa:
An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs. ISQED 2015: 519-523 - 2014
- [j4]Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. 97-D(6): 1546-1556 (2014) - [c31]Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa:
Modeling of substrate contacts in TSV-based 3D ICs. 3DIC 2014: 1-4 - [c30]Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-Aki Fukase, Atsushi Kurokawa:
Impact of on-chip interconnects on vertical signal propagation in 3D ICs. APCCAS 2014: 607-610 - [c29]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura:
An NoC-based evaluation platform for safety-critical automotive applications. APCCAS 2014: 679-682 - [c28]Masashi Imai, Tomohiro Yoneda:
Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. APCCAS 2014: 687-690 - [c27]Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa:
Effect of substrate contacts on reducing crosstalk noise between TSVs. APCCAS 2014: 763-766 - [c26]Masashi Imai, Tomohiro Yoneda:
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. ISCAS 2014: 141-144 - 2013
- [j3]Masashi Imai, Tomohiro Yoneda:
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories. IEICE Trans. Inf. Syst. 96-D(9): 1914-1925 (2013) - 2012
- [c25]Tomohiro Yoneda, Masashi Imai:
Dependable routing in multi-chip NoC platforms for automotive applications. DFT 2012: 217-224 - [c24]Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Multi-chip NoCs for Automotive Applications. PRDC 2012: 105-110 - [c23]Masashi Imai, Tomohiro Yoneda:
Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. PRDC 2012: 111-120 - 2011
- [c22]Masashi Imai, Tomohiro Yoneda:
Improving Dependability and Performance of Fully Asynchronous On-chip Networks. ASYNC 2011: 65-76 - [c21]Masashi Imai, Tomohiro Yoneda:
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. DFT 2011: 463-471 - 2010
- [c20]Masashi Imai, Tomohide Nagai, Takashi Nanya:
Pair and swap: An approach to graceful degradation for dependable chip multiprocessors. DSN Workshops 2010: 119-124 - [c19]James L. Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya:
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors. PRDC 2010: 62-69
2000 – 2009
- 2009
- [c18]Masashi Imai, Kouei Takada, Takashi Nanya:
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. ASYNC 2009: 209-216 - [c17]Masashi Imai, Tomohiro Yoneda, Takashi Nanya:
N-way ring and square arbiters. ICCD 2009: 125-130 - [c16]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 - 2008
- [c15]Masashi Imai, Takashi Nanya:
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ACSD 2008: 21-26 - 2007
- [c14]Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE 2007: 797-802 - 2006
- [j2]Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya:
Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3519-3528 (2006) - [c13]Masashi Imai, Takashi Nanya:
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ASYNC 2006: 68-77 - 2004
- [c12]Masashi Imai, Metehan Özcan, Takashi Nanya:
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ASYNC 2004: 62-71 - [c11]Masayuki Tsukisaka, Masashi Imai, Takashi Nanya:
Asynchronous Scan-Latch controller for Low Area Overhead DFT. ICCD 2004: 66-71 - [c10]Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya:
Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS 2004: 116-125 - 2003
- [j1]Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Özcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3028-3037 (2003) - [c9]Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC 2003: 184-195 - [c8]Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya:
A zero-time-overhead asynchronous four-phase controller. ISCAS (5) 2003: 205-208 - [c7]Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya:
Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) 2003: 617-620 - 2002
- [c6]T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura:
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. APCCAS (1) 2002: 211-216 - [c5]Metehan Özcan, Masashi Imai, Takashi Nanya:
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. ASYNC 2002: 109-114 - [c4]Masayuki Tsukisaka, Masashi Imai, Takashi Nanya:
High Throughput Asynchronous Domino Using Dual output Buffer. IWLS 2002: 279-282 - 2001
- [c3]Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno:
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC 2001: 162-172
1990 – 1999
- 1998
- [c2]Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya:
TITAC-2: An Asynchronous 32-bit Microprocessor. ASP-DAC 1998: 319-320 - 1997
- [c1]Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya:
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ICCD 1997: 288-294
Coauthor Index
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