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ORCIDRoman L. Lysecky
Roman Lysecky
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- affiliation: University of Arizona, Tucson, USA
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2020 – today
- 2024
[c72]Yuchao Liao
, Tosiron Adegbija, Roman Lysecky, Ravi Tandon:
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. ACM Great Lakes Symposium on VLSI 2024: 170-176- [i6]Yuchao Liao, Tosiron Adegbija, Roman Lysecky, Ravi Tandon:
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. CoRR abs/2404.14754 (2024) - [i5]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
A high-level synthesis approach for precisely-timed, energy-efficient embedded systems. CoRR abs/2404.14769 (2024) - [i4]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
Are LLMs Any Good for High-Level Synthesis? CoRR abs/2408.10428 (2024) - [i3]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints. CoRR abs/2408.10431 (2024) - 2023
- [j41]Chelsea Gordon, Roman Lysecky, Frank Vahid:
Less Is More: Students Skim Lengthy Online Textbooks. IEEE Trans. Educ. 66(2): 123-129 (2023) - [c71]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning. ASP-DAC 2023: 567-572 - 2022
- [j40]Aakarsh Rao, Nadir Amin Carreon, Roman Lysecky, Jerzy W. Rozenblit:
FIRE: A Finely Integrated Risk Evaluation Methodology for Life-Critical Embedded Systems. Inf. 13(10): 487 (2022) - [j39]Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
A high-level synthesis approach for precisely-timed, energy-efficient embedded systems. Sustain. Comput. Informatics Syst. 35: 100741 (2022) - [c70]Manoj Gopale, Gregory Ditzler, Roman Lysecky, Janet Roveda:
Inter-Architecture Portability of Artificial Neural Networks and Side Channel Attacks. ACM Great Lakes Symposium on VLSI 2022: 117-121 - 2021
- [j38]Cyril Bresch, David Hély, Stéphanie Chollet, Roman Lysecky:
SecPump: A Connected Open-Source Infusion Pump for Security Research Purposes. IEEE Embed. Syst. Lett. 13(1): 21-24 (2021) - [j37]Bozhi Liu, Kemeng Chen, Minjun Seo, Janet Meiling Roveda, Roman Lysecky:
Methods and Analysis of Automated Trace Alignment Under Power Obfuscation in Side Channel Attacks. J. Hardw. Syst. Secur. 5(2): 127-142 (2021) - [j36]Nadir Amin Carreon, Sixing Lu, Roman Lysecky:
Probabilistic Estimation of Threat Intrusion in Embedded Systems for Runtime Detection. ACM Trans. Embed. Comput. Syst. 20(2): 14:1-14:27 (2021) - [j35]George Gunter, Derek Gloudemans, Raphael E. Stern, Sean T. McQuade, Rahul Bhadani, Matt Bunting, Maria Laura Delle Monache, Roman Lysecky, Benjamin Seibold, Jonathan Sprinkle, Benedetto Piccoli, Daniel B. Work:
Are Commercially Implemented Adaptive Cruise Control Systems String Stable? IEEE Trans. Intell. Transp. Syst. 22(11): 6992-7003 (2021) - [c69]Chelsea Gordon, Roman Lysecky, Frank Vahid:
The shift from static college textbooks to customizable content: A case study at zyBooks. FIE 2021: 1-7 - 2020
- [j34]Adrian Lizarraga, Jonathan Sprinkle, Roman Lysecky:
Automated Model-Based Optimization of Data-Adaptable Embedded Systems. ACM Trans. Embed. Comput. Syst. 19(1): 8:1-8:22 (2020) - [j33]Cyril Bresch, David Hély, Roman Lysecky, Stéphanie Chollet, Ioannis Parissis:
TrustFlow-X: A Practical Framework for Fine-grained Control-flow Integrity in Critical Systems. ACM Trans. Embed. Comput. Syst. 19(5): 36:1-36:26 (2020) - [c68]Nadir Amin Carreon, Allison Gilbreath, Roman Lysecky:
Statistical Time-based Intrusion Detection in Embedded Systems. DATE 2020: 562-567 - [c67]Cyril Bresch, Roman Lysecky, David Hély:
BackFlow: Backward Edge Control Flow Enforcement for Low End ARM Microcontrollers. DATE 2020: 1606-1609
2010 – 2019
- 2019
- [j32]Hyunsuk Nam, Roman Lysecky:
Security-aware multi-objective optimization of distributed reconfigurable embedded systems. J. Parallel Distributed Comput. 133: 377-390 (2019) - [j31]Sixing Lu, Roman Lysecky:
Data-driven Anomaly Detection with Timing Features for Embedded Systems. ACM Trans. Design Autom. Electr. Syst. 24(3): 33:1-33:27 (2019) - [c66]Aakarsh Rao, Nadir Carreón, Roman Lysecky, Jerzy W. Rozenblit, Johannes Sametinger:
Resilient Security of Medical Cyber-Physical Systems. DEXA Workshops 2019: 95-100 - [c65]Frank Vahid, Alex D. Edgcomb, Roman Lysecky, Yamuna Rajasekhar:
New web-based learning content for core programming concepts using Coral. FIE 2019: 1-5 - [c64]Minjun Seo, Roman Lysecky:
Automatic Extraction of Requirements from State-based Hardware Designs for Runtime Verification. ACM Great Lakes Symposium on VLSI 2019: 295-298 - [c63]Tosiron Adegbija, Roman Lysecky, Vinu Vijay Kumar:
Right-Provisioned IoT Edge Computing: An Overview. ACM Great Lakes Symposium on VLSI 2019: 531-536 - [c62]George Gunter, Yanbing Wang, Derek Gloudemans, Raphael E. Stern, Daniel B. Work, Maria Laura Delle Monache, Rahul Bhadani, Matt Bunting, Roman Lysecky, Jonathan Sprinkle, Benjamin Seibold, Benedetto Piccoli:
String stability of commercial adaptive cruise control vehicles: WIP abstract. ICCPS 2019: 328-329 - [c61]Frank Vahid, Roman Lysecky:
Auto-Graded Programming Labs: Dos and Don'ts for Less-Stressed Higher-Performing Students, Reduced Grading Time, and Happier Teachers, . SIGCSE 2019: 1250 - [c60]Nadir Carreon, Allison Gilbreath, Roman Lysecky:
Window-Based Statistical Analysis Of Timing Subcomponents For Efficient Detection Of Malware In Life-Critical Systems. SpringSim 2019: 1-12 - [i2]George Gunter, Derek Gloudemans, Raphael E. Stern, Sean T. McQuade, Rahul Bhadani, Matt Bunting, Maria Laura Delle Monache, Roman Lysecky, Benjamin Seibold, Jonathan Sprinkle, Benedetto Piccoli, Daniel B. Work:
Are commercially implemented adaptive cruise control systems string stable? CoRR abs/1905.02108 (2019) - 2018
- [j30]Hyunsuk Nam, Roman Lysecky:
Mixed Cryptography Constrained Optimization for Heterogeneous, Multicore, and Distributed Embedded Systems. Comput. 7(2): 29 (2018) - [j29]Aakarsh Rao, Nadir Carreon, Roman Lysecky, Jerzy W. Rozenblit:
Probabilistic Threat Detection for Risk Management in Cyber-physical Medical Systems. IEEE Softw. 35(1): 38-43 (2018) - [j28]Sixing Lu, Roman Lysecky:
Time and Sequence Integrated Runtime Anomaly Detection for Embedded Systems. ACM Trans. Embed. Comput. Syst. 17(2): 38:1-38:27 (2018) - [j27]Minjun Seo, Roman Lysecky:
Non-Intrusive In-Situ Requirements Monitoring of Embedded System. ACM Trans. Design Autom. Electr. Syst. 23(5): 58:1-58:27 (2018) - [c59]Minjun Seo, Roman Lysecky:
Runtime requirements monitoring for state-based hardware: work-in-progress. CODES+ISSS 2018: 7 - [c58]Bozhi Liu, Kemeng Chen, Minjun Seo, Janet Meiling Wang, Roman Lysecky:
Evaluation of the Complexity of Automated Trace Alignment using Novel Power Obfuscation Methods. ACM Great Lakes Symposium on VLSI 2018: 467-470 - [c57]Bozhi Liu, Roman Lysecky, Janet Meiling Wang Roveda:
Composable Template Attacks Using Templates for Individual Architectural Components. ICCD 2018: 1-8 - [c56]Nadir Amin Carreon, Sixing Lu, Roman Lysecky:
Hardware-Based Probabilistic Threat Detection and Estimation for Embedded Systems. ICCD 2018: 522-529 - [c55]Nabeel Alzahrani, Frank Vahid, Alex D. Edgcomb, Kevin Nguyen, Roman Lysecky:
Python Versus C++: An Analysis of Student Struggle on Small Coding Exercises in Introductory Programming Courses. SIGCSE 2018: 86-91 - [c54]Roman Lysecky, Frank Vahid:
Teaching Students a Systematic Approach to Debugging: (Abstract Only). SIGCSE 2018: 1104 - [c53]Aakarsh Rao, Jerzy W. Rozenblit, Roman Lysecky, Johannes Sametinger:
Trustworthy multi-modal framework for life-critical systems security. SpringSim (ANSS) 2018: 17:1-17:9 - 2017
- [j26]Nathan Sandoval, Casey Mackin, Sean Whitsitt, Vijay Shankar Gopinath, Sachidanand Mahadevan, Andrew Milakovich, Kyle Merry, Jonathan Sprinkle, Roman Lysecky:
Task Transition Scheduling for Data-Adaptable Systems. ACM Trans. Embed. Comput. Syst. 16(4): 105:1-105:28 (2017) - [c52]Sudarshan Sargur, Roman Lysecky:
Non-intrusive dynamic profiler for multicore embedded systems. ASP-DAC 2017: 500-505 - [c51]Sixing Lu, Roman Lysecky, Jerzy W. Rozenblit:
Subcomponent Timing-Based Detection of Malware in Embedded Systems. ICCD 2017: 17-24 - [c50]Minjun Seo, Roman Lysecky:
Hierarchical Non-intrusive In-situ Requirements Monitoring for Embedded Systems. RV 2017: 259-276 - [c49]Alex D. Edgcomb, Frank Vahid, Roman Lysecky, Susan Lysecky:
Getting Students to Earnestly Do Reading, Studying, and Homework in an Introductory Programming Class. SIGCSE 2017: 171-176 - 2016
- [j25]Minjun Seo, Roman Lysecky:
In-Situ Requirements Monitoring of Embedded Systems. IEEE Embed. Syst. Lett. 8(3): 49-52 (2016) - [c48]Adrian Lizarraga, Roman L. Lysecky, Jonathan Sprinkle:
Model-Driven Optimization of Data-Adaptable Embedded Systems. COMPSAC 2016: 293-302 - [c47]Hyunsuk Nam, Roman Lysecky:
Latency, Power, and Security Optimization in Distributed Reconfigurable Embedded Systems. IPDPS Workshops 2016: 124-131 - 2015
- [j24]Lu Ding, Adrian Lizarraga, Ashish Shenoy, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky:
Application-Specific Customization of Dynamic Profiling Mechanisms for Sensor Networks. IEEE Access 3: 303-322 (2015) - [j23]Johannes Sametinger, Jerzy W. Rozenblit, Roman L. Lysecky, Peter Ott:
Security challenges for medical devices. Commun. ACM 58(4): 74-82 (2015) - [j22]Jong Chul Lee, Roman L. Lysecky:
System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems. ACM Trans. Design Autom. Electr. Syst. 20(3): 42:1-42:27 (2015) - [c46]Sixing Lu, Minjun Seo, Roman Lysecky:
Timing-based anomaly detection in embedded systems. ASP-DAC 2015: 809-814 - [c45]Sixing Lu, Roman Lysecky:
Analysis of Control Flow Events for Timing-based Runtime Anomaly Detection. WESS 2015: 3 - [c44]Alex D. Edgcomb, Frank Vahid, Roman L. Lysecky:
Students learn more with less text that covers the same core topics. FIE 2015: 1-5 - 2014
- [j21]Jong Chul Lee, Jovan Vance, Roman Lysecky:
Hardware-Based Event Stream Ordering for System-Level Observation Framework. IEEE Embed. Syst. Lett. 6(4): 81-84 (2014) - [j20]Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Roveda:
Workload assignment considering NBTI degradation in multicore systems. ACM J. Emerg. Technol. Comput. Syst. 10(1): 4:1-4:22 (2014) - [c43]Jong Chul Lee, Roman Lysecky:
Area-Efficient Event Stream Ordering for Runtime Observability of Embedded Systems. DAC 2014: 130:1-130:6 - 2013
- [j19]Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman Lysecky:
A lightweight dynamic optimization methodology and application metrics estimation model for wireless sensor networks. Sustain. Comput. Informatics Syst. 3(2): 94-108 (2013) - [j18]Jingqing Mu, Karthik Shankar, Roman L. Lysecky:
Profiling and online system-level performance and power estimation for dynamically adaptable embedded systems. ACM Trans. Embed. Comput. Syst. 12(3): 85:1-85:20 (2013) - [j17]Adrian Lizarraga, Roman Lysecky, Susan Lysecky, Ann Gordon-Ross:
Dynamic profiling and fuzzy-logic-based optimization of sensor network platforms. ACM Trans. Embed. Comput. Syst. 13(3): 51:1-51:29 (2013) - [c42]Roman Lysecky, Nathan Sandoval, Sean Whitsitt, Casey Mackin, Jonathan Sprinkle:
Efficient reconfiguration methods to enable rapid deployment of runtime reconfigurable systems. ACSSC 2013: 819-823 - [c41]Jong Chul Lee, Roman Lysecky:
System Observation of Blocking, Non-blocking, and Cascading Events for Runtime Monitoring of Real-Time Systems. ECBS 2013: 49-58 - [c40]Nathan Sandoval, Casey Mackin, Sean Whitsitt, Roman L. Lysecky, Jonathan Sprinkle:
System Throughput Optimization and Runtime Communication Middleware Supporting Dynamic Software-Hardware Task Migration in Data Adaptable Embedded Systems. ECBS 2013: 59-68 - [c39]Lu Ding, Adrian Lizarraga, Susan Lysecky, Roman Lysecky, Ann Gordon-Ross:
Accuracy-Guided Runtime Adaptive Profiling Optimization of Wireless Sensor Networks. ECBS 2013: 82-91 - [c38]Nathan Sandoval, Casey Mackin, Roman L. Lysecky, Jonathan Sprinkle:
How You Can Learn to Stop Worrying and Love Reconfigurable Embedded Systems: A Tutorial. ECBS 2013: 213-214 - [c37]Tim Pifer, David M. Schwartz, Roman Lysecky, Chungman Seo, Bernard P. Zeigler:
Discrete event system specification, synthesis, and optimization of low-power FPGA-based embedded systems. FPT 2013: 98-105 - [c36]Nathan Sandoval, Casey Mackin, Sean Whitsitt, Roman L. Lysecky, Jonathan Sprinkle:
Runtime hardware/software task transition scheduling for data-adaptable embedded systems. FPT 2013: 342-345 - 2012
- [j16]Adrian Lizarraga, Lu Ding, Jeff Hiner, Roman Lysecky, Susan Lysecky, Ann Gordon-Ross:
ATLeS-SN. Des. Autom. Embed. Syst. 16(4): 265-291 (2012) - [j15]Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda:
A self-tuning design methodology for power-efficient multi-core systems. ACM Trans. Design Autom. Electr. Syst. 18(1): 4:1-4:24 (2012) - [c35]Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky:
Online algorithms for wireless sensor networks dynamic optimization. CCNC 2012: 180-187 - [c34]Jingqing Mu, Roman L. Lysecky:
Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systems. CODES+ISSS 2012: 265-274 - [c33]Andrew Milakovich, Vijay Shankar Gopinath, Roman L. Lysecky, Jonathan Sprinkle:
Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems. ECBS 2012: 15-23 - [c32]Varadaraj Kamath Nileshwar, Roman Lysecky:
SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representation. ACM Great Lakes Symposium on VLSI 2012: 27-32 - [c31]Jong Chul Lee, Faycel Kouteib, Roman Lysecky:
Event-driven framework for configurable runtime system observability for SOC designs. ITC 2012: 1-10 - [c30]Sean Whitsitt, Jonathan Sprinkle, Roman L. Lysecky:
An overseer control methodology for data adaptable embedded systems. MPM@MoDELS 2012: 25-30 - 2011
- [j14]Ajay Nair, Karthik Shankar, Roman L. Lysecky:
Efficient hardware-based nonintrusive dynamic application profiling. ACM Trans. Embed. Comput. Syst. 10(3): 32:1-32:22 (2011) - [c29]Jingqing Mu, Roman L. Lysecky:
Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems. ASP-DAC 2011: 737-742 - [c28]Sachidanand Mahadevan, Vijay Shankar Gopinath, Roman L. Lysecky, Jonathan Sprinkle, Jerzy W. Rozenblit, Michael W. Marcellin:
Hardware/Software Communication Middleware for Data Adaptable Embedded Systems. ECBS 2011: 34-43 - [c27]Jong Chul Lee, Andrew S. Gardner, Roman Lysecky:
Hardware Observability Framework for Minimally Intrusive Online Monitoring of Embedded Systems. ECBS 2011: 52-60 - [c26]Vijay Shankar Gopinath, Jonathan Sprinkle, Roman L. Lysecky:
Modeling of Data Adaptable Reconfigurable Embedded Systems. ECBS 2011: 276-283 - 2010
- [j13]Ashish Shenoy, Jeff Hiner, Susan Lysecky, Roman L. Lysecky, Ann Gordon-Ross:
Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks. IEEE Embed. Syst. Lett. 2(1): 10-13 (2010) - [j12]Karthik Shankar, Roman L. Lysecky:
Control Focused Soft Error Detection for Embedded Applications. IEEE Embed. Syst. Lett. 2(4): 127-130 (2010) - [j11]Rahul Kalra, Roman L. Lysecky:
Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 671-674 (2010) - [c25]Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang:
Workload capacity considering NBTI degradation in multi-core systems. ASP-DAC 2010: 450-455 - [c24]Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda:
A self-evolving design methodology for power efficient multi-core systems. ICCAD 2010: 264-268 - [c23]Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan Lysecky, Ann Gordon-Ross:
Transaction-Level Modeling for Sensor Networks Using SystemC. SUTC/UMC 2010: 197-204 - [c22]Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky:
A lightweight dynamic optimization methodology for wireless sensor networks. WiMob 2010: 129-136
2000 – 2009
- 2009
- [j10]Lance Saldanha, Roman L. Lysecky:
Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors. Des. Autom. Embed. Syst. 13(3): 139-157 (2009) - [j9]Roman L. Lysecky, Frank Vahid:
Design and implementation of a MicroBlaze-based warp processor. ACM Trans. Embed. Comput. Syst. 8(3): 22:1-22:22 (2009) - [j8]Jingqing Mu, Roman L. Lysecky:
Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems. ACM Trans. Design Autom. Electr. Syst. 15(1): 2:1-2:20 (2009) - [c21]Karthik Shankar, Roman L. Lysecky:
Non-intrusive dynamic application profiling for multitasked applications. DAC 2009: 130-135 - 2008
- [j7]Frank Vahid, Greg Stitt, Roman L. Lysecky:
Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. Computer 41(7): 40-46 (2008) - [j6]Roman L. Lysecky:
Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning. Int. J. Parallel Program. 36(5): 478-492 (2008) - [c20]Ajay Nair, Roman L. Lysecky:
Non-intrusive dynamic application profiler for detailed loop execution characterization. CASES 2008: 23-30 - [c19]Lance Saldanha, Roman L. Lysecky:
Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits. CODES+ISSS 2008: 49-54 - [c18]Mark Hammerquist, Roman L. Lysecky:
Design space exploration for application specific FPGAS in system-on-a-chip designs. SoCC 2008: 279-282 - 2007
- [c17]Roman L. Lysecky:
Low-power warp processor for power efficient high-performance embedded systems. DATE 2007: 141-146 - [i1]Roman L. Lysecky, Frank Vahid:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. CoRR abs/0710.4705 (2007) - 2006
- [j5]Roman L. Lysecky, Greg Stitt, Frank Vahid:
Warp Processors. ACM Trans. Design Autom. Electr. Syst. 11(3): 659-681 (2006) - [c16]David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen:
Application-specific customization of parameterized FPGA soft-core processors. ICCAD 2006: 261-268 - [c15]David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky:
Conjoining soft-core FPGA processors. ICCAD 2006: 694-701 - 2005
- [c14]Roman L. Lysecky, Frank Vahid:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. DATE 2005: 18-23 - [c13]Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan:
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. FCCM 2005: 57-62 - [c12]Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers:
Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). FPGA 2005: 271 - 2004
- [j4]Chuanjun Zhang, Frank Vahid, Roman L. Lysecky:
A self-tuning cache architecture for embedded systems. ACM Trans. Embed. Comput. Syst. 3(2): 407-425 (2004) - [j3]Roman L. Lysecky, Susan Cotterell, Frank Vahid:
A fast on-chip profiler memory using a pipelined binary tree. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 120-122 (2004) - [c11]Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan:
Dynamic FPGA routing for just-in-time FPGA compilation. DAC 2004: 954-959 - [c10]Chuanjun Zhang, Frank Vahid, Roman L. Lysecky:
A Self-Tuning Cache Architecture for Embedded Systems. DATE 2004: 142-147 - [c9]Roman L. Lysecky, Frank Vahid:
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. DATE 2004: 480-485 - 2003
- [j2]Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt:
Highly configurable platforms for embedded computing systems. Microelectron. J. 34(11): 1025-1029 (2003) - [c8]Roman L. Lysecky, Frank Vahid:
A codesigned on-chip logic minimizer. CODES+ISSS 2003: 109-113 - [c7]Greg Stitt, Roman L. Lysecky, Frank Vahid:
Dynamic hardware/software partitioning: a first approach. DAC 2003: 250-255 - [c6]Roman L. Lysecky, Frank Vahid:
On-chip logic minimization. DAC 2003: 334-337 - 2002
- [j1]Roman L. Lysecky, Frank Vahid:
Prefetching for improved bus wrapper performance in cores. ACM Trans. Design Autom. Electr. Syst. 7(1): 58-90 (2002) - [c5]Roman L. Lysecky, Susan Cotterell, Frank Vahid:
A fast on-chip profiler memory. DAC 2002: 28-33 - 2000
- [c4]Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky:
A first-step towards an architecture tuning methodology for low power. CASES 2000: 187-192 - [c3]Roman L. Lysecky, Frank Vahid, Tony Givargis:
Techniques for Reducing Read Latency of Core Bus Wrappers. DATE 2000: 84-91 - [c2]Roman L. Lysecky, Frank Vahid, Tony Givargis:
Experiments with the Peripheral Virtual Component Interface. ISSS 2000: 221-224
1990 – 1999
- 1999
- [c1]Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis:
Pre-Fetching for Improved Core Interfacing. ISSS 1999: 51-55
Coauthor Index
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