default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID36th ICCD 2018: Orlando, FL, USA
- 36th IEEE International Conference on Computer Design, ICCD 2018, Orlando, FL, USA, October 7-10, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-8477-1
Session 1: Best Papers Session
- Bozhi Liu, Roman Lysecky, Janet Meiling Wang Roveda:
Composable Template Attacks Using Templates for Individual Architectural Components. 1-8 - Deok Keun Oh, Mu Jun Choi, Juho Kim:
Thermal-Aware 3D Symmetrical Buffered Clock Tree Synthesis. 9-16 - Doowon Lee, Opeoluwa Matthews, Valeria Bertacco:
Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems. 17-25 - Xiaofeng Hou, Luoyao Hao
, Chao Li, Quan Chen, Wenli Zheng, Minyi Guo:
Power Grab in Aggressively Provisioned Data Centers: What is the Risk and What Can Be Done About It. 26-34
Session 2A: SSD
- Te I, Murtuza Lokhandwala, Yu-Ching Hu, Hung-Wei Tseng:
Pensieve: a Machine Learning Assisted SSD Layer for Extending the Lifetime. 35-42 - Qiao Li, Liang Shi, Riwei Pan, Cheng Ji, Xiaoqiang Li, Chun Jason Xue:
Selective Compression Scheme for Read Performance Improvement on Flash Devices. 43-50 - Fei Wu, Zuo Lu, You Zhou, Xubin He, Zhi-hu Tan, Changsheng Xie:
OSPADA: One-Shot Programming Aware Data Allocation Policy to Improve 3D NAND Flash Read Performance. 51-58 - Gaoxiang Xu, Zhipeng Tan, Dan Feng, Yifeng Zhu, Xinyan Zhang, Jie Xu:
Cap: Exploiting Data Correlations to Improve the Performance and Endurance of SSD RAID. 59-66
Session 2B: Side Channels
- Elmira Karimi, Zhen Hang Jiang, Yunsi Fei, David R. Kaeli:
A Timing Side-Channel Attack on a Mobile GPU. 67-74 - Mohammad Nasim Imtiaz Khan, Swaroop Ghosh:
Analysis of Row Hammer Attack on STTRAM. 75-82 - David Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead:
Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures. 83-91
Session 3A: Security and Capability
- Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alexander Richardson, Simon W. Moore, Robert N. M. Watson:
CheriRTOS: A Capability Model for Embedded Devices. 92-99 - Joydeep Rakshit, Kartik Mohanram:
ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories. 100-107 - Wenjian He, Wei Zhang, Sanjeev Das, Yang Liu:
SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave Execution. 108-114 - Hamza Omar, Syed Kamran Haider, Ling Ren, Marten van Dijk, Omer Khan:
Breaking the Oblivious-RAM Bandwidth Wall. 115-122
Session 3B: Microarchitecture
- Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando:
Rearranging Random Issue Queue with High IPC and Short Delay. 123-131 - Mustafa Cavus, Resit Sendag, Joshua J. Yi:
Array Tracking Prefetcher for Indirect Accesses. 132-139 - Ricardo Alves, Stefanos Kaxiras, David Black-Schaffer:
Dynamically Disabling Way-prediction to Reduce Instruction Replay. 140-143 - Athanasios Chatzidimitriou, George Papadimitriou, Dimitris Gizopoulos, Shrikanth Ganapathy, John Kalamatianos:
Analysis and Characterization of Ultra Low Power Branch Predictors. 144-147 - Alec Roelke, Xinfei Guo, Mircea Stan:
OldSpot: A Pre-RTL Model for Fine-Grained Aging and Lifetime Optimization. 148-151 - Vignyan Reddy Kothinti Naresh, Rami Sheikh, Arthur Perais, Harold W. Cain:
SPF: Selective Pipeline Flush. 152-155
Session 4A: Logic and Circuit Design 1
- Maedeh Hemmat, Azadeh Davoodi:
Power-Efficient ReRAM-Aware CNN Model Generation. 156-162 - Zhengyu Chen, Hai Zhou, Jie Gu:
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. 163-170 - Alvaro Velasquez, Sumit Kumar Jha:
3D Crosspoint Memory as a Parallel Architecture for Computing Network Reachability. 171-178 - Seyedhamidreza Motaman, Swaroop Ghosh:
Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays. 179-186 - Chiou-Yng Lee, Jiafeng Xie:
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm. 187-194
Session 4B: Design Automation
- Baogang Zhang, Rickard Ewetz:
Software and Hardware Techniques for Reducing the Impact of Quantization Errors in Memristor Crossbar Arrays. 195-201 - Behzad Boroujerdian, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer:
Trading Off Temperature Guardbands via Adaptive Approximations. 202-209 - Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi:
Lattice-Traversing Design Space Exploration for High Level Synthesis. 210-217
Session 5A: Novel Architectures
- Jinhang Choi, Jack Sampson, Vijaykrishnan Narayanan:
Heuristic Approximation of Early-Stage CNN Data Representation for Vision Intelligence Systems. 218-225 - Yue Xu, Hyung Gyu Lee, Xianzhang Chen, Bo Peng, Duo Liu, Liang Liang:
Puppet: Energy Efficient Task Mapping For Storage-Less and Converter-Less Solar-Powered Non-Volatile Sensor Nodes. 226-233 - Kyuin Lee, Vijay Raghunathan, Anand Raghunathan, Younghyun Kim:
SYNCVIBE: Fast and Secure Device Pairing through Physical Vibration on Commodity Smartphones. 234-241 - Joel Mandebi Mbongue, Festus Hategekimana, Danielle Tchuinkou Kwadjo, Christophe Bobda:
FPGA Virtualization in Cloud-Based Infrastructures Over Virtio. 242-245 - Haixin Huang, Kaixin Huang, Litong You, Linpeng Huang:
Forca: Fast and Atomic Remote Direct Access to Persistent Memory. 246-249
Session 5B: Memory 1
- Yongbin Gu, Lizhong Chen:
CART: Cache Access Reordering Tree for Efficient Cache and Memory Accesses in GPUs. 250-257 - Jian Zhou, Jun Wang:
ArchSampler: Architecture-Aware Memory Sampling Library for In-Memory Applications. 258-265 - Adnan Siraj Rakin, Shaahin Angizi, Zhezhi He, Deliang Fan:
PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks. 266-273 - Shuo Li, Zhiguang Chen, Nong Xiao, Guangyu Sun:
Path Prefetching: Accelerating Index Searches for In-Memory Databases. 274-277 - Hao Wen, Wei Zhang:
Reducing Inter-Application Interferences in Integrated CPU-GPU Heterogeneous Architecture. 278-281
Session 6A: Memory 2
- Jeremie S. Kim, Minesh Patel, Hasan Hassan, Onur Mutlu:
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines. 282-291 - Andreas Kurth, Pirmin Vogel, Andrea Marongiu, Luca Benini:
Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine. 292-300 - Yuhai Cao, Chao Li, Quan Chen, Jingwen Leng, Minyi Guo, Jing Wang, Weigong Zhang:
DR DRAM: Accelerating Memory-Read-Intensive Applications. 301-309 - Jee Ho Ryoo, Shuang Song, Lizy K. John:
Puzzle Memory: Multifractional Partitioned Heterogeneous Memory Scheme. 310-317
Session 6B: Logic and Circuit Design 2
- Andrew J. Douglass, Sunil P. Khatri:
Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications. 318-325 - Hye-Yeon Yoon, Tae-Hwan Kim:
Generalized Tree Architecture for Efficient Successive-Cancellation Polar Decoding. 326-333 - Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers:
Parameterized Posit Arithmetic Hardware Generator. 334-341 - Soheil Salehi, Ronald F. DeMara:
BGIM: Bit-Grained Instant-on Memory Cell for Sleep Power Critical Mobile Applications. 342-345 - Siyuan Xu, Benjamin Carrión Schäfer:
Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles. 346-349
Session 7A: Accelerators and GPUs
- Lukas Sommer, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, Andreas Koch:
Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. 350-357 - Kyu Yeun Kim, Woongki Baek:
BLPP: Improving the Performance of GPGPUs with Heterogeneous Memory through Bandwidth- and Latency-Aware Page Placement. 358-365 - Jan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek:
General IDS Acceleration for High-Speed Networks. 366-373 - Siavash Rezaei, Kanghee Kim, Eli Bozorgzadeh:
Scalable Multi-Queue Data Transfer Scheme for FPGA-Based Multi-Accelerators. 374-380
Session 7B: Potpouri 1
- Fei Wu, Yue Zhu, Qin Xiong, Zhonghai Lu, You Zhou, Weizhen Kong, Changsheng Xie:
Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and Applications. 381-388 - Kunal Bharathi, Harsh Kumar, Abbas A. Fairouz, Ahmad Al Kawam, Sunil P. Khatri:
A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability. 389-396 - Huixiang Chen, Yuting Dai, Rui Xue, Kan Zhong, Tao Li:
Towards Efficient Microarchitecture Design of Simultaneous Localization and Mapping in Augmented Reality Era. 397-404 - Sujeong Jo, Hanmin Park, Gunhee Lee, Kiyoung Choi:
Training Neural Networks with Low Precision Dynamic Fixed-Point. 405-408 - Zhongyuan Tian, Haoran Li, Rafael Kioji Vivas Maeda, Jun Feng, Jiang Xu:
Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing. 409-412
Session 8A: NVM
- Amir Saman Memaripour, Steven Swanson:
Breeze: User-Level Access to Non-Volatile Main Memories for Legacy Software. 413-422 - Payman Behnam, Arjun Pal Chowdhury, Mahdi Nazm Bojnordi:
R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays. 423-430 - Fan Yang, Junbin Kang, Shuai Ma, Jinpeng Huai:
A Highly Non-Volatile Memory Scalable and Efficient File System. 431-438 - Xiang Pan, Anys Bacha, Spencer Rudolph, Li Zhou, Yinqian Zhang, Radu Teodorescu:
NVCool: When Non-Volatile Caches Meet Cold Boot Attacks. 439-448
Session 8B: Test and Verification
- Tania Khanna, Michael Hsiao:
Guiding RTL Test Generation Using Relevant Potential Invariants. 449-455 - Zeye Liu, Ronald D. Blanton:
Back-End Layout Reflection for Test Chip Design. 456-463 - Abdullah Ash-Saki, Swaroop Ghosh:
How Multi-Threshold Designs Can Protect Analog IPs. 464-471 - Kunal Bansal, Michael S. Hsiao:
Optimization of Mutant Space for RTL Test Generation. 472-475 - Mohamed A. Neggaz, Ihsen Alouani, Pablo R. Lorenzo, Smaïl Niar:
A Reliability Study on CNNs for Critical Embedded Systems. 476-479
Session 9A: Network on Chip and Synchronization
- Yuechen Chen, Md Farhadur Reza, Ahmed Louri:
DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs. 480-487 - Padmaja Bhamidipati, Avinash Karanth:
RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture. 488-495 - Halit Dogan, Masab Ahmad, José A. Joao, Omer Khan:
Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72. 496-505 - Cunlu Li, Dezun Dong, Xiangke Liao:
Eca-Router : On Achieving Endpoint Congestion Aware Switch Allocation in the On-Chip Network. 506-509 - Dara Rahmati, Sobhan Masoudi, Ahmad Khonsari, Reza Sabbaghi-Nadooshan:
Accurate Performance Bounds Calculation for Dynamic Voltage-Freq Islands in Best Effort NoCs. 510-513
Session 9B: Potpouri 2
- Bikash Poudel, Arslan Munir:
Design and Evaluation of a PVT Variation-Resistant TRNG Circuit. 514-521 - Nadir Amin Carreon, Sixing Lu, Roman Lysecky:
Hardware-Based Probabilistic Threat Detection and Estimation for Embedded Systems. 522-529 - Suyuan Chen, Ranga Vemuri:
Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking. 530-536 - Yingyi Luo, Xiaoyang Wang, Seda Ogrenci Memik, Gokhan Memik, Kazutomo Yoshii, Peter H. Beckman:
Minimizing Thermal Variation in Heterogeneous HPC Systems with FPGA Nodes. 537-544
Session 10A: File System and Cloud
- Qian Zhang, Yongbin Zhou, Shuang Qiu, Wei Cheng, Jingdian Ming, Rui Zhang:
A Compact AES Hardware Implementation Secure Against 1st-Order Side-Channel Attacks. 545-552 - Chunxue Zuo, Fang Wang, Ping Huang, Yuchong Hu, Dan Feng, Yucheng Zhang:
PFCG: Improving the Restore Performance of Package Datasets in Deduplication Systems. 553-560 - Yanwen Xie, Dan Feng, Fang Wang, Xinyan Zhang, Jizhong Han, Xuehai Tang:
OME: An Optimized Modeling Engine for Disk Failure Prediction in Heterogeneous Datacenter. 561-564 - Chuanwen Wang, Diansen Sun, Yunpeng Chai, Fang Zhou:
Enabling Accurate Performance Isolation on Hybrid Storage Devices in Cloud Environment. 565-568 - Ke Zhou, Yu Zhang, Ping Huang, Hua Wang, Yongguang Ji, Bin Cheng, Ying Liu:
LEA: A Lazy Eviction Algorithm for SSD Cache in Cloud Block Storage. 569-572 - Jianmin Qian, Jian Li, Ruhui Ma, Haibing Guan:
Optimizing Virtual Resource Management for Consolidated NUMA Systems. 573-576
Session 10B: FPGA and Machine Learning
- Minghua Shen, Nong Xiao:
Fine-Grained Parallel Routing for FPGAs with Selective Expansion. 577-586 - Siyuan Xu, Benjamin Carrión Schäfer:
DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures. 587-594 - Minghua Shen, Nong Xiao:
Load Balance-Aware Multi-Core Parallel Routing for Large-Scale FPGAs. 595-602 - Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul:
Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis. 603-612
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-13 23:59 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
