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2020 – today
- 2021
[c18]Tomás Fukac, Jirí Matousek, Jan Korenek, Lukás Kekely:
Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks. FPT 2021: 1-9- 2020
- [j2]Michal Kekely, Lukás Kekely
, Jan Korenek:
General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocess. Microsystems 73: 102950 (2020) - [c17]Lukás Kekely, Jakub Cabal, Viktor Pus, Jan Korenek:
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. DSD 2020: 49-56
2010 – 2019
- 2019
- [c16]Lukás Kekely, Jakub Cabal, Jan Korenek:
Effective FPGA Architecture for General CRC. ARCS 2019: 211-223 - 2018
- [c15]Michal Kekely, Lukas Kekely, Jan Korenek:
Memory Aware Packet Matching Architecture for High-Speed Networks. DSD 2018: 1-8 - [c14]Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek:
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. FPGA 2018: 249-258 - [c13]Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek:
Accelerated Wire-Speed Packet Capture at 200 Gbps. FPL 2018: 455-456 - [c12]Jakub Cabal, Lukás Kekely, Jan Korenek:
High-Speed Computation of CRC Codes for FPGAs. FPT 2018: 234-237 - [c11]Lukás Kekely, Martin Spinler, Stepán Friedl, Jiri Sikora, Jan Korenek, Viktor Pus:
Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput. FPT 2018: 381-384 - [c10]Jan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek:
General IDS Acceleration for High-Speed Networks. ICCD 2018: 366-373 - [c9]Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek:
Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers. NOMS 2018: 1-3 - 2016
- [j1]Lukas Kekely, Jan Kucera, Viktor Pus, Jan Korenek, Athanasios V. Vasilakos:
Software Defined Monitoring of Application Protocols. IEEE Trans. Computers 65(2): 615-626 (2016) - 2015
- [c8]Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minarík:
Hardware accelerated flow measurement of 100 Gb ethernet. IM 2015: 1147-1148 - 2014
- [c7]Tomás Závodník, Lukas Kekely, Viktor Pus:
CRC based hashing in FPGA using DSP blocks. DDECS 2014: 179-182 - [c6]Viktor Pus, Lukas Kekely, Jan Korenek:
Design methodology of configurable high performance packet parser for FPGA. DDECS 2014: 189-194 - [c5]Lukas Kekely, Martin Zádník, Jirí Matousek, Jan Korenek:
Fast lookup for dynamic packet filtering in FPGA. DDECS 2014: 219-222 - [c4]Viktor Pus, Lukas Kekely, Tomás Závodník:
Using DSP blocks to compute CRC hash in FPGA (abstract only). FPGA 2014: 256 - [c3]Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek:
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. FPL 2014: 1-4 - [c2]Lukas Kekely, Viktor Pus, Jan Korenek:
Software Defined Monitoring of application protocols. INFOCOM 2014: 1725-1733 - 2012
- [c1]Viktor Pus, Lukas Kekely, Jan Korenek:
Low-latency modular packet header parser for FPGA. ANCS 2012: 77-78
Coauthor Index
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