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2020 – today
- 2023
[c8]Jakub Cabal, Vladislav Válek, Martin Spinler, Daniel Kondys, Jan Korenek:
400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs. INFOCOM Workshops 2023: 1-2- 2022
- [c7]Jakub Cabal, Jiri Sikora, Stepán Friedl, Martin Spinler, Jan Korenek:
FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit. FPL 2022: 474 - 2021
- [c6]Jan Kubálek, Jakub Cabal, Martin Spinler, Radek Isa:
DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers. FCCM 2021: 258 - 2020
- [c5]Lukás Kekely, Jakub Cabal, Viktor Pus, Jan Korenek:
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. DSD 2020: 49-56
2010 – 2019
- 2019
- [c4]Lukás Kekely
, Jakub Cabal, Jan Korenek:
Effective FPGA Architecture for General CRC. ARCS 2019: 211-223 - [c3]Jakub Cabal, Pavel Benácek, Jana Foltova, Juraj Holub:
Scalable P4 Deparser for Speeds Over 100 Gbps. FCCM 2019: 323 - 2018
- [c2]Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek:
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. FPGA 2018: 249-258 - [c1]Jakub Cabal, Lukás Kekely, Jan Korenek:
High-Speed Computation of CRC Codes for FPGAs. FPT 2018: 234-237
Coauthor Index
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