"Low-latency modular packet header parser for FPGA."

Viktor Pus, Lukas Kekely, Jan Korenek (2012)

> Home

Details and statistics

DOI: 10.1145/2396556.2396571

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

- view
  authority control:
- export record
  dblp key:
  - conf/ancs/PusKK12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ancs/PusKK12
Viktor Pus, Lukas Kekely, Jan Korenek:
Low-latency modular packet header parser for FPGA. ANCS 2012: 77-78

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.