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ORCIDZeye Liu 0001
Person information
- affiliation: Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA, USA
Other persons with the same name
- Zeye Liu 0002 — Xi'an Jiaotong University, School of Electronics and Information, China
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2020 – today
- 2023
[j2]Chenlei Fang
, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton:
Efficient Test Chip Design via Smart Computation. ACM Trans. Design Autom. Electr. Syst. 28(2): 22:1-22:31 (2023)- 2020
- [c16]Zeye Liu, R. D. Shawn Blanton:
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips. ITC 2020: 1-10
2010 – 2019
- 2019
- [c15]Ruizhou Ding, Ting-Wu Chin, Zeye Liu, Diana Marculescu:
Regularizing Activation Distribution for Training Binarized Deep Networks. CVPR 2019: 11408-11417 - [c14]Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, R. D. (Shawn) Blanton:
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. DAC 2019: 200 - [c13]Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton:
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design. ICCD 2019: 11-19 - [c12]Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton:
Improving Test Chip Design Efficiency via Machine Learning. ITC 2019: 1-10 - [c11]Danielle Duvalsaint, Zeye Liu, Ananya Ravikumar, Ronald D. Blanton:
Characterization of Locked Sequential Circuits via ATPG. ITC-Asia 2019: 97-102 - [c10]Ben Niewenhuis, Balaji Ravikumar, Zeye Liu, R. D. Shawn Blanton:
Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle. VTS 2019: 1-6 - [i3]Ruizhou Ding, Ting-Wu Chin, Zeye Liu, Diana Marculescu:
Regularizing Activation Distribution for Training Binarized Deep Networks. CoRR abs/1904.02823 (2019) - [i2]Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, Ronald D. Blanton:
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. CoRR abs/1904.02835 (2019) - 2018
- [j1]Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu:
Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. ACM Trans. Reconfigurable Technol. Syst. 11(3): 17:1-17:24 (2018) - [c9]Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu:
Quantized deep neural networks for energy efficient hardware-based inference. ASP-DAC 2018: 1-8 - [c8]Abhinav Goel, Zeye Liu, Ronald D. Blanton:
CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation. IEEE BigData 2018: 4723-4729 - [c7]Zeye Liu, Ronald D. Blanton:
Back-End Layout Reflection for Test Chip Design. ICCD 2018: 456-463 - [i1]Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton:
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. CoRR abs/1802.02178 (2018) - 2017
- [c6]Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton:
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. ACM Great Lakes Symposium on VLSI 2017: 35-40 - [c5]Zeye Liu, Phillip Fynan, Ronald D. Blanton:
Front-end layout reflection for test chip design. ITC 2017: 1-10 - 2016
- [c4]Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton:
Achieving 100% cell-aware coverage by design. DATE 2016: 109-114 - [c3]Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton:
Logic characterization vehicle design reflection via layout rewiring. ITC 2016: 1-10 - [c2]Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton:
Test chip design for optimal cell-aware diagnosability. ITC 2016: 1-8 - 2015
- [c1]R. D. (Shawn) Blanton, Benjamin Niewenhuis, Zeye (Dexter) Liu:
Design reflection for optimal test-chip implementation. ITC 2015: 1-10
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