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ORCIDYamuna Rajasekhar
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2010 – 2019
- 2019
[c9]Nikitha Sambamurthy, Alex D. Edgcomb, Yamuna Rajasekhar:
Student Usage of Interactive Learning Tools in an Online Linear Circuit Analysis Textbook. FIE 2019: 1-6- [c8]Frank Vahid, Alex D. Edgcomb, Roman Lysecky, Yamuna Rajasekhar:
New web-based learning content for core programming concepts using Coral. FIE 2019: 1-5 - 2014
- [j1]Yamuna Rajasekhar, Ron Sass:
Architecture and applications for an All-FPGA parallel computer. Clust. Comput. 17(2): 315-325 (2014) - 2013
- [c7]Yamuna Rajasekhar, Ron Sass:
A Novel Memory Subsystem and Computational Model for Parallel Reconfigurable Architectures. Euro-Par Workshops 2013: 444-453 - 2012
- [c6]Yamuna Rajasekhar, Rahul R. Sharma, Ron Sass:
An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems. FCCM 2012: 117-120 - [c5]Yamuna Rajasekhar, Ron Sass:
Architecture and Applications for an All-FPGA Parallel Computer. ICPP Workshops 2012: 157-164 - [c4]Rahul R. Sharma, Yamuna Rajasekhar, Ron Sass:
Exploring hardware work queue support for lightweight threads in MPSoCs. ReConFig 2012: 1-6 - 2011
- [c3]William V. Kritikos, Yamuna Rajasekhar, Andrew G. Schmidt, Ron Sass:
A Radix Tree Router for Scalable FPGA Networks. FPL 2011: 76-81
2000 – 2009
- 2008
- [c2]Yamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, Ron Sass:
FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAs. FCCM 2008: 298-299 - [c1]Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass:
Teaching FPGA system design via a remote laboratory facility. FPL 2008: 687-690
Coauthor Index
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