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ORCIDDaniel J. Sorin
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- affiliation: Duke University, Durham, USA
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2020 – today
- 2024
[c75]An Qi Zhang
, Andrés Goens, Nicolai Oswald, Tobias Grosser, Daniel J. Sorin, Vijay Nagarajan:
PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model. PACT 2024: 1-13- [c74]Weihang Li, Andrés Goens, Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin:
Determining the Minimum Number of Virtual Networks for Different Coherence Protocols. ISCA 2024: 182-197 - [i8]Beyza Dabak, Major Glenn, Jingyang Liu, Alexander Buck, Siyi Yang, A. Robert Calderbank, Natalie Enright Jerger, Daniel J. Sorin:
Low-Energy Line Codes for On-Chip Networks. CoRR abs/2405.14783 (2024) - 2023
- [j26]Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo X. Olausson, Reece Carr:
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. IEEE Micro 43(4): 62-70 (2023) - [c73]Filip Mazurek, Arya Tschand, Yu Wang, Miroslav Pajic, Daniel J. Sorin:
Rigorous Evaluation of Computer Processors with Statistical Model Checking. MICRO 2023: 1242-1254 - 2022
- [c72]Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo Olausson, Reece Carr:
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. HPCA 2022: 756-771 - [c71]Atefeh Mehrabi, Daniel J. Sorin, Benjamin C. Lee:
Spatiotemporal Strategies for Long-Term FPGA Resource Management. ISPASS 2022: 198-209 - 2021
- [j25]Daniel J. Sorin:
Reconfigurable Hardware in Postsilicon Microarchitecture. Computer 54(3): 4-5 (2021) - [j24]Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin:
Bayesian Optimization for Efficient Accelerator Synthesis. ACM Trans. Archit. Code Optim. 18(1): 4:1-4:25 (2021) - [c70]Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, Mike O'Connor:
Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures. ISPASS 2021: 48-58 - 2020
- [b3]Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood:
A Primer on Memory Consistency and Cache Coherence, Second Edition. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2020, ISBN 978-3-031-00636-4 - [j23]Daniel J. Sorin:
Computer Architecture for Orbital Edge Computing. Computer 53(4): 7-8 (2020) - [c69]Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin:
Prospector: Synthesizing Efficient Accelerators via Statistical Learning. DATE 2020: 151-156 - [c68]Samantha Archer, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin:
Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory. DSN 2020: 331-342 - [c67]Sean Murray, George Dimitri Konidaris, Daniel J. Sorin:
Roadmap Subsampling for Changing Environments. IROS 2020: 5664-5670 - [c66]Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin:
HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols. ISCA 2020: 888-899
2010 – 2019
- 2019
- [c65]Sean Murray, Will Floyd-Jones, George Dimitri Konidaris, Daniel J. Sorin:
A Programmable Architecture for Robot Motion Planning Acceleration. ASAP 2019: 185-188 - [c64]Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin:
GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors. DSN 2019: 1-12 - 2018
- [j22]Daniel J. Sorin:
Low-Power Content Addressable Memory. Computer 51(3): 8-9 (2018) - [j21]Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin:
Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2462-2473 (2018) - [c63]Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin:
ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications. ISCA 2018: 247-260 - 2017
- [j20]Daniel J. Sorin:
Persistent Memory. Computer 50(3): 12 (2017) - [c62]Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Derek R. Hower, Daniel J. Sorin:
Jenga: Efficient Fault Tolerance for Stacked DRAM. ICCD 2017: 361-368 - [c61]Opeoluwa Matthews, Daniel J. Sorin:
Architecting hierarchical coherence protocols for push-button parametric verification. MICRO 2017: 477-489 - [i7]Alireza Vahid, Georgios Mappouras, Daniel J. Sorin, A. Robert Calderbank:
Correcting Two Deletions and Insertions in Racetrack Memory. CoRR abs/1701.06478 (2017) - 2016
- [j19]Milo M. K. Martin, Daniel J. Sorin:
Top Picks from the 2015 Computer Architecture Conferences. IEEE Micro 36(3): 6-9 (2016) - [c60]Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin:
Methuselah Flash: Rewriting Codes for Extra Long Storage Lifetime. DSN 2016: 180-191 - [c59]Opeoluwa Matthews, Jesse D. Bingham, Daniel J. Sorin:
Verifiable hierarchical protocols with network invariants on parametric systems. FMCAD 2016: 101-108 - [c58]Sean Murray, William Floyd-Jones, Ying Qi, George Dimitri Konidaris, Daniel J. Sorin:
The microarchitecture of a real-time robot motion planning accelerator. MICRO 2016: 45:1-45:12 - [c57]Sean Murray, Will Floyd-Jones, Ying Qi, Daniel J. Sorin, George Dimitri Konidaris:
Robot Motion Planning on a Chip. Robotics: Science and Systems 2016 - [i6]Ralph Nathan, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun:
Profile-Driven Automated Mixed Precision. CoRR abs/1606.00251 (2016) - [i5]Blake A. Hechtman, Andrew D. Hilton, Daniel J. Sorin:
TREES: A CPU/GPU Task-Parallel Runtime with Explicit Epoch Synchronization. CoRR abs/1608.00571 (2016) - 2015
- [j18]Ralph Nathan, Daniel J. Sorin:
Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores. IEEE Comput. Archit. Lett. 14(1): 13-16 (2015) - [j17]Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin:
PVCoherence: Designing Flat Coherence Protocols for Scalable Verification. IEEE Micro 35(3): 84-91 (2015) - [c56]Adam N. Jacobvitz, Andrew D. Hilton, Daniel J. Sorin:
Multi-program benchmark definition. ISPASS 2015: 72-82 - [c55]Ali Eslami, Alfredo Velasco, Alireza Vahid, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin:
Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design. MEMSYS 2015: 71-77 - [i4]Yaqi Zhang, Ralph Nathan, Daniel J. Sorin:
Reduced Precision Checking to Detect Errors in Floating Point Arithmetic. CoRR abs/1510.01145 (2015) - 2014
- [c54]Daniel J. Sorin, Opeoluwa Matthews, Meng Zhang:
Architecting Dynamic Power Management to be Formally Verifiable. DAC 2014: 3:1-3:3 - [c53]Ralph Nathan, Daniel J. Sorin:
Nostradamus: Low-cost hardware-only error detection for processor cores. DATE 2014: 1-6 - [c52]Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin:
PVCoherence: Designing flat coherence protocols for scalable verification. HPCA 2014: 392-403 - [c51]Opeoluwa Matthews, Meng Zhang, Daniel J. Sorin:
Scalably verifiable dynamic power management. HPCA 2014: 579-590 - [c50]Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun:
Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. SC 2014: 117-127 - 2013
- [c49]Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin:
Coset coding to extend the lifetime of memory. HPCA 2013: 222-233 - [c48]Blake A. Hechtman, Daniel J. Sorin:
Exploring memory consistency for massively-threaded throughput-oriented processors. ISCA 2013: 201-212 - [c47]Blake A. Hechtman, Daniel J. Sorin:
Evaluating cache coherent shared virtual memory for heterogeneous multicore chips. ISPASS 2013: 118-119 - [c46]Kushal Seetharam, Lance Ong-Siong Co Ting Keh, Ralph Nathan, Daniel J. Sorin:
Applying Reduced Precision Arithmetic to Detect Errors in Floating Point Multiplication. PRDC 2013: 232-235 - [i3]Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun:
Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point. CoRR abs/1309.7321 (2013) - [i2]Blake A. Hechtman, Daniel J. Sorin:
Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips. CoRR abs/1310.7792 (2013) - 2012
- [j16]Milo M. K. Martin, Mark D. Hill, Daniel J. Sorin:
Why on-chip cache coherence is here to stay. Commun. ACM 55(7): 78-89 (2012) - [c45]Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin:
Writing cosets of a convolutional code to increase the Lifetime of Flash memory. Allerton Conference 2012: 308-318 - 2011
- [b2]Daniel J. Sorin, Mark D. Hill, David A. Wood:
A Primer on Memory Consistency and Cache Coherence. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2011, ISBN 978-3-031-01733-9 - [j15]Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin:
Address Translation Aware Memory Consistency. IEEE Micro 31(1): 109-118 (2011) - [c44]Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, Arijit Biswas, Xavier Vera:
Architectures for online error detection and recovery in multicore processors. DATE 2011: 533-538 - [c43]Patrick J. Eibl, Albert Meixner, Daniel J. Sorin:
An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2. SIGMETRICS 2011: 121-122 - 2010
- [j14]Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin:
Fractal Consistency: Architecting the Memory System to Facilitate Verification. IEEE Comput. Archit. Lett. 9(2): 61-64 (2010) - [c42]Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin:
Specifying and dynamically verifying address translation-aware memory consistency. ASPLOS 2010: 323-334 - [c41]Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy:
UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. HPCA 2010: 1-12 - [c40]Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin:
Fractal Coherence: Scalably Verifiable Cache Coherence. MICRO 2010: 471-482
2000 – 2009
- 2009
- [b1]Daniel J. Sorin:
Fault Tolerant Computer Architecture. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2009, ISBN 978-3-031-00595-4 - [j13]Albert Meixner, Daniel J. Sorin:
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. IEEE Trans. Dependable Secur. Comput. 6(1): 18-31 (2009) - [c39]Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin:
Reduced Precision Checking for a Floating Point Adder. DFT 2009: 145-152 - [c38]Meng Zhang, Anita Lungu, Daniel J. Sorin:
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms. DFT 2009: 277-285 - [c37]Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin:
Dynamic power gating with quality guarantees. ISLPED 2009: 377-382 - [c36]Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen:
Multicore power management: Ensuring robustness via early-stage formal verification. MEMOCODE 2009: 78-87 - 2008
- [j12]Albert Meixner, Michael E. Bauer, Daniel J. Sorin:
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. IEEE Micro 28(1): 52-59 (2008) - [j11]Fred A. Bower, Daniel J. Sorin, Landon P. Cox:
The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling. IEEE Micro 28(3): 17-25 (2008) - [c35]Bogdan F. Romanescu, Daniel J. Sorin:
Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. PACT 2008: 43-51 - [c34]Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin:
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. Conf. Computing Frontiers 2008: 129-138 - [c33]Albert Meixner, Daniel J. Sorin:
Detouring: Translating software to circumvent hard faults in simple cores. DSN 2008: 80-89 - 2007
- [j10]Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin:
VariaSim: simulating circuits and systems in the presence of process variability. SIGARCH Comput. Archit. News 35(5): 45-48 (2007) - [j9]Fred A. Bower, Daniel J. Sorin, Sule Ozev:
Online diagnosis of hard faults in microprocessors. ACM Trans. Archit. Code Optim. 4(2): 8 (2007) - [c32]Anita Lungu, Daniel J. Sorin:
Verification-Aware Microprocessor Design. PACT 2007: 83-93 - [c31]Albert Meixner, Daniel J. Sorin:
Error Detection Using Dynamic Dataflow Verification. PACT 2007: 104-118 - [c30]Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev:
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. PACT 2007: 424 - [c29]Albert Meixner, Daniel J. Sorin:
Unified microprocessor core storage. Conf. Computing Frontiers 2007: 23-34 - [c28]Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin:
Lazy Error Detection for Microprocessor Functional Units. DFT 2007: 361-369 - [c27]Albert Meixner, Daniel J. Sorin:
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures. HPCA 2007: 145-156 - [c26]Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz:
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. ICCD 2007: 317-324 - [c25]Albert Meixner, Michael E. Bauer, Daniel J. Sorin:
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. MICRO 2007: 210-222 - [i1]Jonathan R. Carter, Sule Ozev, Daniel J. Sorin:
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. CoRR abs/0710.4715 (2007) - 2006
- [j8]Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin:
NANA: A nano-scale active network architecture. ACM J. Emerg. Technol. Comput. Syst. 2(1): 1-30 (2006) - [j7]Tong Li, Alvin R. Lebeck, Daniel J. Sorin:
Spin Detection Hardware for Improved Management of Multithreaded Systems. IEEE Trans. Parallel Distributed Syst. 17(6): 508-521 (2006) - [c24]Albert Meixner, Daniel J. Sorin:
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. DSN 2006: 73-82 - [c23]Nathan Sadler, Daniel J. Sorin:
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. ICCD 2006: 499-505 - [c22]Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin:
Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. ITC 2006: 1-10 - [c21]Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev:
Applying architectural vulnerability Analysis to hard faults in the microprocessor. SIGMETRICS/Performance 2006: 375-376 - 2005
- [j6]Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin:
Self-Assembled Architectures and the Temporal Aspects of Computing. Computer 38(1): 56-64 (2005) - [j5]Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood:
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News 33(4): 92-99 (2005) - [j4]Fred A. Bower, Sule Ozev, Daniel J. Sorin:
Autonomic Microprocessor Execution via Self-Repairing Arrays. IEEE Trans. Dependable Secur. Comput. 2(4): 297-310 (2005) - [c20]Jonathan R. Carter, Sule Ozev, Daniel J. Sorin:
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. DATE 2005: 300-305 - [c19]Albert Meixner, Daniel J. Sorin:
Dynamic Verification of Sequential Consistency. ISCA 2005: 482-493 - [c18]Fred A. Bower, Daniel J. Sorin, Sule Ozev:
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. MICRO 2005: 197-208 - [c17]Tong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin:
Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution. USENIX ATC, General Track 2005: 31-44 - 2004
- [c16]Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin:
Tolerating Hard Faults in Microprocessor Array Structures. DSN 2004: 51-60 - [c15]Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood:
Using Speculation to Simplify Multiprocessor Design. IPDPS 2004 - [c14]Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin:
Communication breakdown: analyzing CPU usage in commercial Web workloads. ISPASS 2004: 12-19 - 2003
- [j3]Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, Daniel J. Sorin:
Simulating a $2M Commercial Server on a $2K PC. Computer 36(2): 50-57 (2003) - [j2]Daniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon:
Analytic Evaluation of Shared-Memory Architectures. IEEE Trans. Parallel Distributed Syst. 14(2): 166-180 (2003) - [c13]Daniel J. Sorin, Mark D. Hill, David A. Wood:
Dynamic Verification of End-to-End Multiprocessor Invariants. DSN 2003: 281-290 - [c12]Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood:
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. ISCA 2003: 206-217 - [c11]Tong Li, Alvin R. Lebeck, Daniel J. Sorin:
Quantifying instruction criticality for shared memory multiprocessors. SPAA 2003: 128-137 - 2002
- [j1]Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood:
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. IEEE Trans. Parallel Distributed Syst. 13(6): 556-578 (2002) - [c10]Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood:
Bandwidth Adaptive Snooping. HPCA 2002: 251-262 - [c9]Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood:
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. ISCA 2002: 123-134 - 2001
- [c8]Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti:
Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. MICRO 2001: 328-337 - 2000
- [c7]Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood:
Timestamp snooping: an approach for extending SMPs. ASPLOS 2000: 25-36 - [c6]Derek L. Eager, Daniel J. Sorin, Mary K. Vernon:
AMVA techniques for high service time variability. SIGMETRICS 2000: 217-228
1990 – 1999
- 1999
- [c5]Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin:
Using Lamport Clocks to Reason about Relaxed Memory Models. HPCA 1999: 270-278 - [c4]E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood:
Multicast Snooping: A New Coherence Method Using a Multicast Address Network. ISCA 1999: 294-304 - [c3]Mark D. Hill, Anne Condon, Manoj Plakal, Daniel J. Sorin:
A System-Level Specification Framework for I/O Architectures. SPAA 1999: 138-147 - 1998
- [c2]Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood:
Analytic Evaluation of Shared-memory Systems with ILP Processors. ISCA 1998: 380-391 - [c1]Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D. Hill:
Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. SPAA 1998: 67-76
Coauthor Index
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