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ORCIDVLSI Design, Volume 2011
Volume 2011, 2011
- Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto:
Buffer Planning for IP Placement Using Sliced-LFF. 530851:1-530851:10 - Usha Sandeep Mehta
, Kankar S. Dasgupta, Niranjan M. Devashrayee:
Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey. 948926:1-948926:7 - Nancy Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan:
Shedding Physical Synthesis Area Bloat. 503025:1-503025:10 - Jacqueline E. Rice, Jon C. Muzio, Neil Anderson:
New Considerations for Spectral Classification of Boolean Switching Functions. 356137:1-356137:9 - Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
The Impact of Statistical Leakage Models on Design Yield Estimation. 471903:1-471903:12 - Dongjin Lee, Igor L. Markov:
CONTANGO: Integrated Optimization of SoC Clock Networks. 407507:1-407507:12 - Debasri Saha, Susmita Sur-Kolay:
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection. 731957:1-731957:10 - Yoni Aizik, Avinoam Kolodny:
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints. 845957:1-845957:13 - Mohammad Asad R. Chaudhry, Zakia Asad, Alexander Sprintson, Jiang Hu:
Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies. 892310:1-892310:9 - T. Suresh, K. L. Shunmuganathan:
Efficient Resource Sharing Architecture for Multistandard Communication System. 328640:1-328640:9 - Subhra Dhar, Manisha Pattanaik, Poolla Rajaram:
Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications. 178516:1-178516:19 - Tareq Hasan Khan, Khan A. Wahid:
Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy. 343787:1-343787:12 - Haipeng Zhang, Ruisheng Qi, Liang Zhang, Buchun Su, Dejun Wang:
Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity. 548546:1-548546:9 - Guanyi Sun, Shengnan Xu, Xu Wang, Dawei Wang, Eugene Tang, Yangdong Deng, Sun Chan:
A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips. 726014:1-726014:17 - Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. 475952:1-475952:17 - Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee:
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method. 756561:1-756561:8 - I. Hameem Shanavas, Ramaswamy Kannan Gnanamurthy:
Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms. 896241:1-896241:9 - Shiyan Hu, Zhuo Li, Yangdong Deng:
CAD for Gigascale SoC Design and Verification Solutions. 398390:1-398390:2
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