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ORCIDChittaranjan A. Mandal
Chittaranjan Mandal 0001 – Chitta Mandal
Person information
- affiliation: ERNET, India
Other persons with the same name
- Chittaranjan Mandal 0002
![[0000-0002-5228-7002]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-5228-7002")
(aka: Chittaranjan R. Mandal) — Indian Institute of Technology, Department of Computer Science and Engineering, Kharagpur, India
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2020 – today
- 2022
[j26]Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Holger Giese:
Translation validation of coloured Petri net models of programs on integers. Acta Informatica 59(6): 725-759 (2022)
2010 – 2019
- 2019
- [j25]Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal:
Equivalence checking of Petri net models of programs using static and dynamic cut-points. Acta Informatica 56(4): 321-383 (2019) - [j24]Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal:
Verification of parallelising transformations of KPN models. IET Cyper-Phys. Syst.: Theory & Appl. 4(3): 276-289 (2019) - [c54]Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal:
SamaTulyataOne: A Path Based Equivalence Checker. ISEC 2019: 21:1-21:5 - 2018
- [i3]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. CoRR abs/1810.10412 (2018) - [i2]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. CoRR abs/1810.12789 (2018) - [i1]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. CoRR abs/1811.05161 (2018) - 2017
- [j23]Jasaswi Prasad Mohanty, Chittaranjan A. Mandal, Chris Reade:
Distributed construction of minimum Connected Dominating Set in wireless sensor network using two-hop information. Comput. Networks 123: 137-152 (2017) - [j22]Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal:
Deriving bisimulation relations from path based equivalence checkers. Formal Aspects Comput. 29(2): 365-379 (2017) - [j21]Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal:
Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers. IEEE Trans. Software Eng. 43(10): 946-953 (2017) - [c53]Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar:
An Equivalence Checking Framework for Array-Intensive Programs. ATVA 2017: 84-90 - [c52]Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan A. Mandal:
SamaTulyata: An Efficient Path Based Equivalence Checking Tool. ATVA 2017: 109-116 - 2016
- [j20]Jasaswi Prasad Mohanty, Chittaranjan A. Mandal, Chris Reade, Ariyam Das:
Construction of minimum connected dominating set in wireless sensor networks using pseudo dominating set. Ad Hoc Networks 42: 61-73 (2016) - [j19]Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Kunal Banerjee, Krishnam Raju Duddu:
A Path Construction Algorithm for Translation Validation Using PRES+ Models. Parallel Process. Lett. 26(2): 1650010:1-1650010:18 (2016) - [c51]Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal:
An efficient path based equivalence checking for Petri net based models of programs. ISEC 2016: 70-79 - [c50]Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar:
Translation validation of loop and arithmetic transformations in the presence of recurrences. LCTES 2016: 31-40 - [c49]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
An early global routing framework for uniform wire distribution in SoCs. SoCC 2016: 139-144 - [c48]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. VLSID 2016: 595-596 - 2015
- [c47]Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal:
Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs. ICSE (2) 2015: 827-828 - [c46]Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal:
A Path-based Equivalence Checking Method for Petri Net based Models of Programs. ICSOFT-EA 2015: 319-329 - [c45]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
A New Method for Defining Monotone Staircases in VLSI Floorplans. ISVLSI 2015: 107-112 - [c44]Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar:
Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking. ISVLSI 2015: 183-186 - [c43]Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal:
Validating SPARK: High Level Synthesis Compiler. ISVLSI 2015: 195-198 - [c42]K. K. Sharma, Kunal Banerjee, Chittaranjan A. Mandal:
Establishing Equivalence of Expressions: An Automated Evaluator Designer's Perspective. MIKE 2015: 415-423 - [c41]Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar:
A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs. SCAM 2015: 247-252 - [c40]K. K. Sharma, Kunal Banerjee, Chittaranjan A. Mandal:
Determining Equivalence of Expressions: An Automated Evaluator's Perspective. T4E 2015: 35-36 - 2014
- [j18]Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal:
Verification of Code Motion Techniques Using Value Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1180-1193 (2014) - [j17]Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal:
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 2015-2019 (2014) - [c39]Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay:
Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks. DSD 2014: 520-527 - [c38]Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar:
Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers. VDAT 2014: 1-6 - [c37]Partha De, Kunal Banerjee, Chittaranjan A. Mandal:
A BDD based secure hardware design method to guard against power analysis attacks. VDAT 2014: 1-2 - [c36]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Global Routing Using Monotone Staircases with Minimal Bends. VLSID 2014: 369-374 - 2013
- [j16]Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal:
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1787-1800 (2013) - [c35]Ariyam Das, Chittaranjan A. Mandal, Chris Reade:
Determining the User Intent Behind Web Search Queries by Learning from Past User Interactions with Search Results. COMAD 2013: 135-138 - [c34]Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay:
Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic. DSD 2013: 641-644 - [c33]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Global routing using monotone staircase channels. ISVLSI 2013: 90-95 - [c32]Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal:
Verification of KPN Level Transformations. VLSI Design 2013: 338-343 - 2012
- [j15]Priyankar Ghosh, Aritra Hazra, Rahul Gonnabhaktula, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul:
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads. J. Low Power Electron. 8(3): 293-303 (2012) - [j14]Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar:
Formal verification of code motion techniques using data-flow-driven equivalence checking. ACM Trans. Design Autom. Electr. Syst. 17(3): 30:1-30:37 (2012) - [c31]Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal:
A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. ISED 2012: 67-71 - [c30]Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal:
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker. VDAT 2012: 69-78 - [c29]Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta, Chittaranjan A. Mandal:
Workload Driven Power Domain Partitioning. VDAT 2012: 147-155 - [c28]Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal:
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. VDAT 2012: 327-336 - 2011
- [j13]Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. VLSI Design 2011: 475952:1-475952:17 (2011) - [c27]Priyankar Ghosh, Aritra Hazra, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul:
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads. ISED 2011: 273-278 - [c26]Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal:
Equivalence Checking of Array-Intensive Programs. ISVLSI 2011: 156-161 - [c25]Chandan Karfa, Chitta Mandal, Dipankar Sarkar:
Verification of Register Transfer Level Low Power Transformations. ISVLSI 2011: 313-314 - [c24]Ariyam Das, Chittaranjan A. Mandal, Chris Reade, Manish Aasawat:
An improved greedy construction of minimum connected dominating sets in wireless networks. WCNC 2011: 790-795 - 2010
- [j12]Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. Integr. 43(3): 289-304 (2010) - [j11]Chandan Karfa, Dipankar Sarkar, Chitta Mandal:
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 479-492 (2010) - [j10]Rajiv Misra, Chittaranjan A. Mandal:
Minimum Connected Dominating Set Using a Collaborative Cover Heuristic for Ad Hoc Sensor Networks. IEEE Trans. Parallel Distributed Syst. 21(3): 292-302 (2010) - [c23]Gopal Paul, Rohit Reddy, Chittaranjan A. Mandal, Bhargab B. Bhattacharya:
A BDD-Based Design of an Area-Power Efficient Asynchronous Adder. ISVLSI 2010: 29-34 - [c22]Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal:
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI 2010: 428-433 - [c21]Gopal Paul, Santosh Biswas, Chittaranjan A. Mandal, Bhargab B. Bhattacharya:
A BDD-based approach to design power-aware on-line detectors for digital circuits. SoCC 2010: 343-346
2000 – 2009
- 2009
- [j9]Rajiv Misra, Chittaranjan A. Mandal:
Rotation of CDS via Connected Domatic Partition in Ad Hoc Sensor Networks. IEEE Trans. Mob. Comput. 8(4): 488-499 (2009) - [j8]Rajiv Misra, Chittaranjan A. Mandal:
Efficient clusterhead rotation via domatic partition in self-organizing sensor networks. Wirel. Commun. Mob. Comput. 9(8): 1040-1058 (2009) - [c20]Rajiv Misra, Chittaranjan A. Mandal:
Location Updates of Mobile Node in Wireless Sensor Networks. MSN 2009: 311-318 - [c19]Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
Systematic Methodology for High-Level Performance Modeling of Analog Systems. VLSI Design 2009: 361-366 - 2008
- [j7]Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar:
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 556-569 (2008) - [j6]Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra:
A Fast Exploration Procedure for Analog High-Level Specification Translation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1493-1497 (2008) - 2007
- [j5]Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade:
A System for Automatic Evaluation of C Programs: Features and Interfaces. Int. J. Web Based Learn. Teach. Technol. 2(4): 24-39 (2007) - [c18]Rajiv Misra, Chittaranjan A. Mandal:
ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks. COMSWARE 2007 - [c17]Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade:
Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI 2007: 429-434 - [c16]Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade:
Register Sharing Verification During Data-Path Synthesis. ICCTA 2007: 135-140 - [c15]Vinay Vishwakarma, Chittaranjan A. Mandal, Shamik Sural:
Automatic Detection of Human Fall in Video. PReMI 2007: 616-623 - [c14]Chittaranjan A. Mandal, Chris Reade:
Recipient Specific Electronic Cash - A Scheme for Recipient Specific Yet Anonymous and Tranferable Electronic Cash. WEBIST (3) 2007: 204-209 - 2006
- [c13]Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra:
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. DATE 2006: 1203-1204 - [c12]Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
A formal approach for high level synthesis of linear analog systems. ACM Great Lakes Symposium on VLSI 2006: 345-348 - [c11]Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade:
A Formal Verification Method of Scheduling in High-level Synthesis. ISQED 2006: 71-78 - [c10]Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade:
Verification of Scheduling in High-level Synthesis. ISVLSI 2006: 141-146 - [c9]Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade:
A System for Automatic Evaluation of Programs for Correctness and Performance. WEBIST (2) 2006: 196-203 - [c8]Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade:
A System for Automatic Evaluation of Programs for Correctness and Performance. WEBIST (Selected Papers) 2006: 367-380 - [c7]Chittaranjan A. Mandal, Chris Reade:
Animating Algorithms over the Web. WEBIST (2) 2006: 403-407 - 2004
- [c6]Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal:
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. DATE 2004: 1198-1203 - 2002
- [c5]Bipin Rajendran, Veerbhan Kheterpal, Abhishek Das, Jayanta Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti:
Timing analysis of tree-like RLC circuits. ISCAS (4) 2002: 838-841 - 2000
- [j4]Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 747-750 (2000) - [c4]Chittaranjan A. Mandal, R. M. Zimmer:
A Genetic Algorithm for the Synthesis of Structured Data Paths. VLSI Design 2000: 206-211
1990 – 1999
- 1999
- [j3]Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
A design space exploration scheme for data-path synthesis. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 331-338 (1999) - 1998
- [j2]Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose:
Complexity of Scheduling in High Level Synthesis. VLSI Design 7(4): 337-346 (1998) - 1997
- [c3]Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
Design Space Exploration for Data Path Synthesis. VLSI Design 1997: 166-173 - 1996
- [c2]Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. VLSI Design 1996: 122-125 - 1992
- [j1]Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
Register-interconnect optimization in data path synthesis. Microprocess. Microprogramming 33(5): 279-288 (1992) - [c1]Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose:
Interconnect Optimization Techniques in Data Path Synthesis. VLSI Design 1992: 85-90
Coauthor Index
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