"Verification of Datapath and Controller Generation Phase in High-Level ..."

Chandan Karfa, Dipankar Sarkar, Chitta Mandal (2010)

> Home

Details and statistics

DOI: 10.1109/TCAD.2009.2035542

access: closed

type: Journal Article

metadata version: 2021-03-08

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/KarfaSM10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/KarfaSM10
Chandan Karfa, Dipankar Sarkar, Chitta Mandal:
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 479-492 (2010)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.