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2010 – 2019
- 2016
[j1]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan
, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer:
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits 51(1): 230-239 (2016)- 2015
- [c4]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns:
17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. ISSCC 2015: 1-3 - 2013
- [c3]John Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner:
7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. ISSCC 2013: 324-325
2000 – 2009
- 2006
- [c2]John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr:
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC 2006: 2564-2571 - 2000
- [c1]Doug Malone, Paul Bunce, Joe DellaPietro, John Davis, James Dawson, Thomas J. Knips, Don Plass, Phil Pritzlaff, Kenneth Reyer:
Design validation of .18 μm 1 GHz cache and register arrays. CICC 2000: 295-298
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